Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-10-09
2003-04-15
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S341000, C257S401000
Reexamination Certificate
active
06548863
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention regards a lateral DMOS transistor integratable in semiconductor power devices.
2. Description of the Related Art
As is known, lateral DMOS transistors are extensively used in semiconductor power devices on account of the ease with which they may be connected to the other components making up the device and on account of their low resistance.
One of the major problems encountered in the fabrication of lateral DMOS transistors is represented by the fact that high electrical fields are set up on their surfaces, for example in the vicinity of their gate regions, which may cause early breakdown of said transistors.
To reduce the surface electrical fields various solutions have been proposed. Among these, a technique currently used is illustrated in M. Zitouni, F. Morancho, P. Rossel, H. Tranduc, J. Buxo, and I. Pagès, “A New Concept for the Lateral DMOS Transistor for Smart Power IC's”, Proceedings of ISPSD 99, Toronto, Ontario, Canada, May 26-28. This technique envisages the formation, in the epitaxial layer housing the body and drain regions of the lateral DMOS transistor, beneath the gate region, of an insulating region having a U-shaped cross section, which is filled with oxide. The insulating region may extend in depth as far as approximately one half of the thickness of the epitaxial layer. In such conditions, the equipotential lines of the surface electrical field remain confined within the insulating region, and the charge-depletion region surrounding the junction made up of the body region and the epitaxial region does not extend very far in the direction of the drain region. This enables high breakdown voltages (up to 69 V) to be achieved with reduced dimensions. However, in certain applications higher performance levels are required, with higher breakdown voltages given the same dimensions, or else smaller dimensions given the same breakdown voltages.
SUMMARY OF THE INVENTION
An embodiment of the present invention is to provides a lateral DMOS transistor that will improve the performance levels that are obtainable from known transistors.
The lateral DMOS transistor is integratable in semiconductor power devices, and includes a P-type substrate and an N-type epitaxial layer. The lateral DMOS transistor comprises a source region and a drain region formed in the epitaxial layer and a body region housing the source region. Between the source region and the drain region is present an insulating region extending in depth from a top surface of the epitaxial layer as far as the substrate. The insulating region presents an interruption in a longitudinal direction defining a channeling region for a current I
D
flowing between the source region and the drain region of the lateral DMOS transistor.
REFERENCES:
patent: 4796070 (1989-01-01), Black
patent: 5349224 (1994-09-01), Gilbert et al.
patent: 5569949 (1996-10-01), Malhi
patent: 11103056 (1999-04-01), None
Zitouni et al., “A New Concept for the Lateral DMOS Transistor for Smart Power IC's,” IEEE: 73-76, 1999.
Bennett II Harold H.
Jorgenson Lisa K.
Seed IP Law Group PLLC
STMicroelectronics S.r.l.
Tran Long
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