Lateral DMOS FET device with reduced on resistance

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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257338, 257343, 257401, 257750, H01L 2978

Patent

active

051929899

ABSTRACT:
A lateral DMOS FET device which has a small on resistance. The device includes a cell structure formed by a plurality of unit cells, each unit cell including: a source region of first conduction type formed on one side of a substrate of first conduction type; a channel region of second conduction type formed around the source region; and a plurality of drain contact regions of first conduction type located around the channel region; and a source electrode, a gate electrode, and a drain electrode, all of which are formed on the same one side of the substrate. Alternatively, each unit cell may includes: a drain contact region of first conduction type formed on one side of a substrate of first conduction type; a channel region of second conduction type formed around the drain contact region; and a plurality of source regions of first conduction type located around the channel region.

REFERENCES:
patent: 4148047 (1979-04-01), Hendrickson
patent: 4794432 (1988-12-01), Yilmaz et al.
patent: 4890142 (1989-12-01), Tonnel et al.
patent: 4901131 (1990-02-01), Takahashi
patent: 4920397 (1990-04-01), Ishijima
patent: 4982249 (1991-01-01), Kim et al.
patent: 4998156 (1991-03-01), Goodman et al.
Electronic Engineering, Feb. 1983, "Siliconix undercuts power Mosfet Industry", page 15.

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