Lateral diffused metal oxide semiconductor (LDMOS) devices...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257S401000, C257SE29261, C257SE27060

Reexamination Certificate

active

08063444

ABSTRACT:
Lateral diffused metal oxide semiconductor (LDMOS) devices with electrostatic discharge (ESD) protection capability are presented for integrated circuits. The LDMOS device includes a semiconductor substrate with an epi-layer thereon. Patterned isolations are disposed on the epi-layer, thereby defining a first active region and a second active region. An N-type double diffused drain (NDDD) region is formed in the first active region and a N+doped drain region is disposed in the NDDD region. A P-body diffused region is formed in the second active region, wherein the NDDD region and the P-body diffused region are separated with a predetermined distance exposing the epi-layer. An N+doped source region and a P+diffused region are disposed in the P-body diffused region. A gate structure is disposed between the N+doped source region and the N+doped drain region. An additional heavily doped region is formed between the semiconductor and the epi-layer. The punch-through voltage or the breakdown voltage of the interface can be adapted by regulating the P+ or N+ dosage to exceed the breakdown voltage of the LDNMOS transistor or the LDPMOS transistor. It can be able to effectively reduce the breakdown voltage or the punch-through voltage relative to the semiconductor substrate under the drain region, thus increasing ESD protection.

REFERENCES:
patent: 6395591 (2002-05-01), McCormack et al.
patent: 6933559 (2005-08-01), Van Roijen et al.
patent: 2006/0124994 (2006-06-01), Jang et al.
patent: 2007/0007591 (2007-01-01), Theeuwen et al.
Liu, Y.Q. et al., “Improving the ESD Performance of LDMOS Device with New NBL,” Electronic Product Reliability and Enviromental Testing, Jun. 30, 2008, pp. 9-14, vol. 26, No. 3, China.
Ming-Dou Ker et al., “Double Snapback Characteristics in High-Voltage nMOSFETs and the Impact to On-Chip ESD Protection Design,” IEEE Electron Device Letters, Sep. 30, 2004, pp. 12-14, vol. 25, No. 9, IEEE, US.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Lateral diffused metal oxide semiconductor (LDMOS) devices... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Lateral diffused metal oxide semiconductor (LDMOS) devices..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Lateral diffused metal oxide semiconductor (LDMOS) devices... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4288846

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.