Active solid-state devices (e.g. – transistors – solid-state diode – With means to increase breakdown voltage threshold – In integrated circuit
Reexamination Certificate
2001-06-26
2004-09-07
Wilczewski, Mary (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
With means to increase breakdown voltage threshold
In integrated circuit
C257S493000
Reexamination Certificate
active
06787872
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to semiconductor devices and more specifically relates to a novel lateral conduction superjunction MOSFET device.
BACKGROUND OF THE INVENTION
MOSFET superjunction devices are well known and are disclosed in U.S. Pat. Nos. 4,754,310 and 5,216,275 and in a publication entitled “Simulated Superior Performance of Semiconductor Superjunction Devices” by Fujihara and Miyaska in the Proceedings of 1998 International Symposium on Semiconductor Devices & ICs, pages 423 to 426. Such superjunction devices have required deep trenches or sequentially deposited and diffused P and N epitaxially layers of silicon. Further, the operational characteristics of prior superjunction devices have not been optimized.
BRIEF DESCRIPTION OF THE INVENTION
In accordance with a first feature of the invention, a lightly conductive P
−
substrate is provided, and an N
−
epitaxial layer and then a P
−
epitaxial layer are grown on the P
−
substrate. Laterally elongated and spaced trenches are formed from the top of the P
−
epitaxial region and extend down and slightly into the N
−
substrate. The trenches define P
−
mesas between them. An N
−
diffusion liner is then diffused into the walls and bottom of the trenches. The trenches are then filled with silicon dioxide insulation. The N
−
diffusion liner has a resurf concentration of 1E12 ions per cm
2
over the full exposed N-trench area. The P
−
pillars have a concentration of 2E12 ions/cm
2
.
In other embodiments of the invention, the P
−
epi layer can be formed on an SOI (Silicon on Insulator) substrate.
The novel structure of the invention provides a number of advantages over prior art devices:
1. A shallower trench is needed to fabricate the device. Thus, a 15 micron deep trench can be used in place of a prior art 35 micron trench for a 600 volt device.
2. A denser structure can be made, using a 1 micron pitch. Since pitch is proportional to on-resistance R
DSON
the reduction of pitch is very desirable.
3. Since the device is a lateral conduction device, it will have a reduced gate charge Q
g
which is essential to many applications.
4. The novel structure of the invention lends itself to the integration of plural devices in a common chip, for example, a bridge circuit can be integrated into a single chip.
5. The device can act as a high side switch when the N
−
layer is designed to support the rail voltage between source and substrate. High side devices, low side devices and control circuitry can then be integrated into the same silicon.
REFERENCES:
patent: 4605948 (1986-08-01), Martinelli
patent: 4754310 (1988-06-01), Coe
patent: 5233215 (1993-08-01), Baliga
patent: 5323040 (1994-06-01), Baliga
patent: 5436173 (1995-07-01), Houston
patent: 5449946 (1995-09-01), Sakakibara et al.
patent: 5539238 (1996-07-01), Malhi
patent: 5592005 (1997-01-01), Floyd et al.
patent: 5679966 (1997-10-01), Baliga et al.
patent: 5710455 (1998-01-01), Bhatnagar et al.
patent: 5801431 (1998-09-01), Ranjan
patent: 5844275 (1998-12-01), Kitamura et al.
patent: 5861657 (1999-01-01), Ranjan
patent: 5874767 (1999-02-01), Terashima et al.
patent: 5885878 (1999-03-01), Fujishima et al.
patent: 6040600 (2000-03-01), Uenishi et al.
patent: 6069396 (2000-05-01), Funaki
patent: 6307246 (2001-10-01), Nitta et al.
patent: 2002/0130358 (2002-09-01), Van Dalen et al.
patent: 2002/0177277 (2002-11-01), Baliga
Kinzer Daniel M.
Sridevan Srikant
International Rectifier Corporation
Lewis Monica
Ostrolenk Faber Gerb & Soffen, LLP
Wilczewski Mary
LandOfFree
Lateral conduction superjunction semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Lateral conduction superjunction semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Lateral conduction superjunction semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3206221