Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Lateral bipolar transistor structure
Reexamination Certificate
1999-05-19
2002-04-23
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Lateral bipolar transistor structure
C257S347000, C257S558000, C257S559000, C257S571000, C257S586000, C257S592000
Reexamination Certificate
active
06376897
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
This invention relates to a bipolar transistor and, more particularly, to a lateral bipolar semiconductor device made by using semiconductor thin films like SOI (silicon on insulator) layer on an insulating substrate.
Bipolar transistor (hereinafter called “BJT”) made by using SOI layers are expected to be operative at a higher speed because of the lower floating capacitance as compared with transistors made on bulk silicon substrates. One of literatures disclosing such BJT is, for example, IEEE EDL-8, No. 3, p. 104, 1987 by J. C. Sturm, et al.
FIG. 49
is a schematic cross-sectional view showing construction of BJT. BJT shown here is formed on an insulating film
2
stacked on a silicon substrate
1
. That is, made on the insulating film
2
are an n
+
-type collector region
67
, p-type intrinsic base region
63
and n
+
-type emitter region
68
in a close alignment in this order. Made on the intrinsic base region
63
in self alignment is a p
+
-type external base region
63
2
for ensuring contact with an electrode.
A manufacturing method of this structure is summarized below. First made on the insulating film
2
is an initial silicon layer having a thickness approximately reaching the surface of a p
+
-type layer
63
2
, and an impurity is doped into the entirety to the impurity concentration of the intrinsic base region
63
. Then, its surface is doped into a p
+
-type, and a thick insulating film is made in the region for the base region. Using this film as a mask, regions for the emitter and the collector are etched until removing the p
+
-type layer. Still using the thick insulating film as a mask, an n-type impurity is doped into the emitter and collector regions by ion implantation.
In the structure shown in
FIG. 49
, even if the base contact is made on the external base region
63
2
at one end of the element located in a vertical direction relative to the drawing sheet, electric bias from the contact to the intrinsic base region
63
results in being first transferred through the external base region
63
2
having a relatively low resistance, and then being supplied from an upper direction to a lower direction. Therefore, by enlarging the intrinsic base region
63
and the external base region
63
2
in width and by elongating the device along a direction vertical to the drawing sheet, the cross-sectional area vertical to the flow direction of the base current in the intrinsic base region and the external base region can be increased, and the base resistance can be decreased. The decrease of the base resistance leads to improvement of noise figure (NF) and maximum oscillation frequency (f
max
) which are important performance indices for use of BJT as an analog element, and BJT having low-noise high f
max
characteristics could be expected.
However, for use with high frequencies on the order of gigaherz, another performance index, the cut-off frequency (f
T
), must be improved. Actually, as shown in the following equation, the value of f
T
is closely related with NF and f
max
, and high f
T
is indispensable also for good NF and f
max
.
f
max
=
f
T
8
π
R
B
C
jc
N
F
=
1
+
q
I
c
R
B
k
T
(
f
f
T
)
2
[
1
+
1
+
2
k
T
q
I
c
R
B
(
f
T
f
)
2
]
where R
B
is the base resistance, C
jc
is the capacitance between the base and the collector, q is the elementary charge I
c
is the collector current, T is the absolute temperature, k is the Boltzmann constant, f is the frequency.
Therefore, in order to obtain high f
T
by reducing the carrier transit time in the base region, the width of the intrinsic base region
63
(distance from the emitter-side end to the collector-side end) must be reduced as small as 0.1 &mgr;m or less.
This width cannot be sufficiently reduced due to dimensional limitation of lithography process. Even if it could be reduced, since it compels the overlying p
+
-type region to be narrowed, the base resistance of the external base region
63
2
increases, and sufficient NF and f
max
could not be obtained.
On the other hand, as a literature disclosing a structure for supplying a base bias from an upper portion, there is a report in IEDM Tech. Dig. p. 663 (1991) by G. G. Shahidi, et al.
FIG. 50
is a cross-sectional view schematically showing BJT using the structure. A feature of this BJT lies in using p-type polycrystalline silicon (polysilicon)
163
for extension of the electrode from the base p-type region
63
toward the upper portion, and connecting it to low-resistance p
+
-type polysilicon
63
2
. This p
+
-type polysilicon
63
2
is separated from the n
−
-type collector region by the insulating layer
169
and insulating side walls
168
.
In this structure, since the intrinsic base and the external base are made independently to permit the external base to be made with a sufficient width even when the intrinsic base is narrowed, there is a possibility of overcoming the problem involved in the structure shown in FIG.
49
.
In the structure of
FIG. 50
, however, since the lead-out portion
163
connecting the intrinsic base and the external base is made of a different material of polycrystalline silicon and so on, for example, it results in having contact resistance between the intrinsic base and the lead-out layer and between the lead-out layer and the external base respectively. Furthermore, the lead-out portion is made of polycrystalline silicon with a higher specific resistance than single crystalline silicon with the same impurity concentration. Therefore, actual base resistance increases significantly. In order to decrease the base resistance, there is the need for some additional measures, such as further increasing the length in the direction vertical to the drawing sheet, connecting a plurality of BJTs in parallel, for example, and its results in increasing the area each element occupies and increasing power consumption.
At the contact between the intrinsic base and the lead-out portion, the device property is liable to deteriorate due to turbulence in impurity profile. More specifically, if the impurity concentration in the lead-out is increased higher than that of the intrinsic base for the purpose of reducing the contact resistances and the resistance of the lead-out portion itself, impurities diffuse from the high-concentrated lead-out portion to the intrinsic base, and invites an increase in base concentration near the interface and an increase in the base width. As a result, current gain factor (h
FE
) and f
T
may decrease, and the junction with the high-concentrated emitter may deteriorate to permit tunneling junction leakage. In contrast, when the impurity concentration in the lead-out portion is lower than that of the intrinsic base, the base resistance increases, and impurities in the single-crystal silicon are rather absorbed out along the interface. Therefore, punch-through is liable to occur. Furthermore, since the depletion region extending from the emitter and collector to the base crosses over the lead-out portion along the contact interface, it may invites some additional problems, such as sudden increase in junction leakage, deterioration of the withstanding voltage, and so on.
To prevent these problems, it is necessary to set the width of the intrinsic base wider than that of the lead-out portion as illustrated in the drawing, and this inevitably invites a decrease of f
T
. In contrast, if the intrinsic base is narrowed, the lead-out portion must be more narrowed, and it results in increasing the base lead-out resistance. Therefore, it has been very difficult to improve the total performance.
There is a possibility of overcoming some of the above-indicated problems by making the base lead-out portion as a single crystal silicon layer by selective epitaxial growth instead of polycrystalline silicon. In this case, however, there will remain the same problems as those with polysil
Fuse Tsuneaki
Inoh Kazumi
Kawanaka Shigeru
Nii Hideaki
Shino Tomoaki
Kabushiki Kaisha Toshiba
Loke Steven
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
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