Latency counter having frequency detector and latency...

Details Latency counter having frequency detector and latency... Latency counter having frequency detector and latency...

2007-10-09

2007-10-09

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Signals

C365S233100, C327S149000, C327S158000

Reexamination Certificate

active

11556195

ABSTRACT:
The present invention discloses a latency counter applied to a memory, for delaying a memory accessing control signal. The latency counter includes: a clock delay module for applying at least one delay amount to the input clock to generate a delayed input clock; a frequency detector for detecting a frequency of a specific signal of the memory to set the delay amount; and a delay control signal generating module for generating a first delayed control signal and a second delayed control signal corresponding to the delayed input clock and the memory accessing control signal respectively, wherein timing of the first delayed control signal is earlier than timing of the second delayed control signal.

REFERENCES:
patent: 5498990 (1996-03-01), Leung et al.
patent: 5831467 (1998-11-01), Leung et al.
patent: 6687185 (2004-02-01), Keeth et al.
patent: 6968025 (2005-11-01), Tanahashi
patent: 7092480 (2006-08-01), Younis
patent: 2005/0105349 (2005-05-01), Dahlberg

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