Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1996-10-17
1999-02-16
Fourson, George R.
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438432, H01L 2176
Patent
active
058720448
ABSTRACT:
Trenches 72 are formed in substrate 17 late in the fabrication process. In order to avoid trench sidewall stresses that cause defects in the substrate monocrystalline lattice, the trenches are filled after a final thick thermal oxide layer, such as a LOCOS layer 25, is grown. The trenches 72 are also filled after a final deep diffusion, i.e. a diffusion in excess of one micron.
REFERENCES:
patent: 4140558 (1979-02-01), Murphy et al.
patent: 4549927 (1985-10-01), Goth et al.
patent: 4631803 (1986-12-01), Hunter et al.
patent: 4839309 (1989-06-01), Easter et al.
patent: 4884117 (1989-11-01), Neppl et al.
patent: 4987471 (1991-01-01), Easter et al.
patent: 5027184 (1991-06-01), Soclof
patent: 5100830 (1992-03-01), Morita
patent: 5141888 (1992-08-01), Kawaji et al.
patent: 5173436 (1992-12-01), Gill et al.
patent: 5200348 (1993-04-01), Uchida et al.
patent: 5217919 (1993-06-01), Gaul et al.
patent: 5241211 (1993-08-01), Tashiko
patent: 5315144 (1994-05-01), Cherne
patent: 5434446 (1995-07-01), Hilton et al.
Hemmenway Donald Frank
Pearce Lawrence George
Fourson George R.
Harris Corporation
LandOfFree
Late process method for trench isolation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Late process method for trench isolation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Late process method for trench isolation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2062057