Latching method

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit

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Details

327203, 327218, H03K 3356

Patent

active

059907177

ABSTRACT:
A high-performance flip-flop circuit implementation. The flip-flop circuit comprises an "implicit" one-shot to generate a delayed clock output (407). The flip-flop comprises a delay block (405) coupled to a clock input (210). The flip-flop may be a D-type flip-flop. In a positive-edge-triggered embodiment of the flip-flop, a falling edge (540) of the delayed clock output (407) follows a rising edge (544) of a clock signal after a delay period (548). The flip-flop clocks in new data at a data input (205) in response to the clock input (210) during this delay period (548). Data is held in a storage block (450). The flip-flop has extremely good transient characteristics, especially set-up and clock-to-output times. The flip-flop consumes no static power.

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Bowhill William, "A 300 MHz 64b Quad-Issue CMOS RISC Microprocessor," 1995 IEEE International Solid-State Circuits Conference entitled Digest of Technical Papers, First Edition, Catalogue No. 95CH35753, Session 10, Microprocessors, Paper TP 10.7, pp. 182-183, 362.
Chappell Terry, "A 2-ns Cycle, 3.8-ns Access 512-kb CMOS ECL SRAM With a Fully Pipelined Architecture," IEEE Journal of Solid-State Circuits, vol. 26, No. 11, Nov. 1991, pp. 1577-1585.
Dobberpuhl Daniel, "A 200-MHz 64-b Dual-Issue CMOS Microprocessor," IEEE Journal of Solid-State Circuits, vol. 27, No. 11, Nov. 1992, pp. 1555-1567 .

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