Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
2000-02-25
2001-08-28
Nguyen, Tan T. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S203000, C327S052000, C327S057000
Reexamination Certificate
active
06282138
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates in general to semiconductor memory devices and, more specifically, to latched sense amplifiers in such memory devices having pre-charge circuitry and tri-state outputs.
2. State of the Art
As shown in
FIG. 1
, in general, a conventional sense amplifier
10
known from Seki, et al., “A 6-ns 1-Mb CMOS SRAM with Latched Sense Amplifier,” IEEE Journal of Solid-State Circuits, Vol. 28, No. 4, pp. 478-483 (1993), receives logic bits output from memory cells (not shown) on complementary bitline bus conductors LD
1
and LD
2
, amplifies the received logic bits at latch output nodes NODE
1
and NODE
2
, and outputs the amplified logic bits onto internal data bus conductors (not shown). Output buffers (not shown) connected to the internal data bus conductors then output the logic bits for use by external circuitry (not shown), such as a microprocessor.
More specifically, the sense amplifier
10
begins an operation cycle when an equalization signal SP goes high and turns on equalization NMOS transistors
12
and
14
, thereby equalizing electric charge stored on latch output nodes NODE
1
and NODE
2
and on internal nodes NODE
3
and NODE
4
. Shortly thereafter, a sense amplifier enabling signal SAC goes high and turns on a current source NMOS transistor
16
, thus enabling latching circuitry
18
of the sense amplifier
10
. At the same time, the equalized stored charge on latch output nodes NODE
1
and NODE
2
induces a voltage on these nodes of approximately half the supply voltage V
CC
(i.e., V
CC
/2), which is of sufficient magnitude to moderately turn on sourcing NMOS transistors
20
and
22
.
With the latching circuitry
18
enabled, the equalization signal SP goes low to turn off the equalization NMOS transistors
12
and
14
. In this state of the sense amplifier
10
, the latch output nodes NODE
1
and NODE
2
are isolated from one another, allowing the sense amplifier
10
to latch in a logic bit from the bitline bus conductors LD
1
and LD
2
when it appears.
A logic bit from a memory cell (not shown) appears in a complementary fashion on the bitline bus conductors LD
1
and LD
2
, with one of the conductors LD
1
and LD
2
having a voltage of approximately half the supply voltage V
CC
(i.e., V
CC
/2), and the other having the same voltage less about 200 millivolts (mV) (i.e., (V
CC
/2)−200 mV). Thus, a logic “1” bit appears as an approximately 200 mV difference in voltages on the bitline bus conductors LD
1
and LD
2
, with the bitline bus conductor LD
1
having the higher voltage. Similarly, a logic “0” bit also appears as an approximately 200 mV difference in voltages on the bitline bus conductors LD
1
and LD
2
, but with the bitline bus conductor LD
2
having the higher voltage.
When a logic “1” bit, for example, appears on the bitline bus conductors LD
1
and LD
2
for latching into the sense amplifier
10
, the voltages on the bitline bus conductors LD
1
and LD
2
representing the logic “1” bit turn on driving transistors
24
and
26
, with the higher voltage on the bitline bus conductor LD
1
turning on the driving transistor
24
more than the lower voltage on the bitline bus conductor LD
2
turns on the driving transistor
26
. Because the driving transistor
24
is on more than the driving transistor
26
, the charge stored on the latch output node NODE
1
drains to ground through the transistors
24
,
20
, and
16
more rapidly than the charge stored on the latch output node NODE
2
can drain to ground through the transistors
26
,
22
, and
16
. As a result, the voltage on the latch output node NODE
1
drops more rapidly than the voltage on the latch output node NODE
2
.
This more-rapidly-dropping voltage on the latch output node NODE
1
causes a PMOS load transistor
28
and a sourcing PMOS transistor
30
to turn on, thereby pulling the latch output node NODE
2
substantially to the supply voltage V
CC
. The supply voltage V
CC
on the latch output node NODE
2
then turns the sourcing NMOS transistor
20
fully on, and causes a PMOS load transistor
32
and a sourcing PMOS transistor
34
to be off, thereby causing the transistors
24
,
20
, and
16
to rapidly drain any remaining charge on the latch output node NODE
1
to ground so that the voltage on the latch output node NODE
1
is substantially at ground. In turn, the ground voltage on the latch output node NODE
1
turns the PMOS load transistor
28
and sourcing PMOS transistor
30
fully on, thereby reinforcing the supply voltage V
CC
on the latch output node NODE
2
. In this state of the latching circuitry
18
, the logic “1” bit is latched in. Of course, if the logic bit is a logic “0” bit, the latching circuitry
18
latches in the logic bit in the opposite manner.
The Seki, et al. sense amplifier
10
of
FIG. 1
generally latches in a logic bit more rapidly than many sense amplifiers that preceded it. Still, it is desirable to have a sense amplifier that latches in logic bits even more rapidly to further improve the speed with which the logic bits may be read from semiconductor memory devices.
SUMMARY OF THE INVENTION
The present invention recognizes that the conventional Seki, et al. sense amplifier described above does not latch in logic bits as rapidly as it could. This is because the Seki, et al. sense amplifier latches in a logic bit, in part, by pulling one of its latch output nodes up to a supply voltage V
CC
from a voltage approximately intermediate the supply voltage V
CC
and ground. The time it takes for the Seki, et al. sense amplifier to pull one of its latch output nodes up to the supply voltage V
CC
is excess sensing time that is substantially eliminated by the present invention.
A sense amplifier in accordance with the present invention includes a differential amplifier having a pair of differential input terminals that receives bitline bus signal and its complement (i.e., receives logic “1” or “0” bit in a complementary manner) and a pair of differential outputs terminals that output the bitline bus signal and its complement in a differentiated manner. Pre-charge circuitry selectively pre-charges the input and output terminals of the differential amplifier to, for example, the supply voltage V
CC
, and a pair of complementary output terminals of a tri-state output circuit coupled to the differential amplifier outputs an internal data bus signal and its complement in response to the differentiated bitline bus signal and its differentiated complement. So the sense amplifier can share the internal data bus with other sense amplifiers, the complementary output terminals of the tri-state output circuit are capable of attaining a high-impedance state when the sense amplifier is inactive.
Because the inventive sense amplifier pre-charges the output terminals of its differential amplifier to, for example, the supply voltage V
CC
, no time is wasted pulling one of those terminals up during sensing, in contrast to the Seki, et al. sense amplifier previously described. Thus, the present invention provides a sense amplifier that rapidly latches in logic bits in order to improve the speed with which the logic bits may be read from semiconductor memory devices.
In other embodiments of the present invention, the sense amplifier described above is incorporated into a memory device, such as a Static Random Access Memory (SRAM), an electronic system, and a semiconductor wafer.
In still another embodiment, a method for increasing the sensing speed of a sense amplifier that has a differential amplifier with outputs that achieve a high or a low voltage during sensing of a logic bit includes pre-charging the outputs substantially to the high voltage prior to sensing the logic bit. As a result, the logic bit may be sensed more rapidly.
In yet another embodiment, a bitline bus signal and its complement are sensed by providing first and second complementary nodes at which a difference in voltage between the bitline bus signal and its complement may be amplified so one of the nodes is at a hig
Micro)n Technology, Inc.
Nguyen Tan T.
TraskBritt
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