Static information storage and retrieval – Addressing – Including particular address buffer or latch circuit...
Reexamination Certificate
2000-08-30
2001-08-14
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Addressing
Including particular address buffer or latch circuit...
C365S189070, C365S230060
Reexamination Certificate
active
06275443
ABSTRACT:
BACKGROUND OF THE INVENTION
I. Field of the Invention
The present invention relates generally to a device and method for semiconductor memory devices employing redundant elements. In particular, the present invention relates to minimizing circuitry for enabling or disabling a column select signal for a primary column in a memory array.
II. Description of the Related Art
In order to ensure proper operation, semiconductor devices are typically tested before being packaged into a chip. A series of probes on a test station electrically contact pads on each die to access portions of the individual semiconductor devices on the die. For example, in a semiconductor memory device, the probes contact address pads and data input/output pads to access selected memory cells in the memory device. Typical dynamic random access memory (“DRAM”) devices include one or more arrays of memory cells arranged in columns and rows. Each array of memory cells includes word or column lines that select memory cells along a selected column, and bit or row lines (or pairs of lines) that select individual memory cells along a column to read data from, or write data to, the cells in the selected column.
During a primary pretest, predetermined data or voltage values arc typically written to selected column and row addresses that correspond to certain memory cells, and then the voltage values are read from those memory cells determine if the read data matches the data written to those addresses. If the read data does not match the written data, then the memory cells at the selected addresses likely contain defects and the semiconductor device fails the test.
Many semiconductor devices, particularly memory devices, include redundant circuitry on the semiconductor device that can be employed to compensate for certain detected failures. As a result, by enabling such redundant circuitry, the device need not be discarded even if it fails a particular pretest. For example, memory devices typically employ redundant columns and rows of memory cells so that if a memory cell in a column or row of the primary memory array is defective, then an entire column or row, or segments thereof, of redundant memory cells can be substituted therefor, respectively.
Substitution of one of the redundant columns or rows or segments thereof is conventionally accomplished by programming fuses or antifuses in a bank of latch devices to select redundant columns or rows or segments to replace defective primary columns or rows. Each bank represents a memory address. If a given primary column or row in the array contains a defective memory cell, then the die can be moved to a station where programming of the fuses or antifuses is accomplished to produce a binary output matching the defective address. For example, if the defective primary column or row has an 8-bit binary address of 00100100, appropriate fuses or antifuses in a bank of 8 are programmed to store this address.
Conventionally, as shown in
FIG. 1
which shows a redundant select circuit for a column, when an address in the memory device is accessed, a column address compare circuit
100
compares an incoming address to addresses stored in the fuse or antifuse banks to determine whether the incoming address matches an address containing a defective memory cell. If the column address compare circuit
100
determines such a match, then it outputs a match signal
150
to a controller in a column decoder
200
. In response, the column decoder
200
causes an appropriate redundant column to be accessed, and disables the column select signal
250
, thus disabling the column drive signal
350
for the defective primary column in the memory array
400
each time a match is found with a redundant column. (Each primary column
400
has a dedicated column latch
300
.) The column decoder
200
goes through this procedure each and every time the memory device receives an incoming address pertaining to its primary column
400
. If the column address compare circuit
100
does not find a match with a redundant column, the column decoder
200
enables the column select signal
250
to provide the column latch
300
with a column select signal
250
to enable a column drive signal
350
to access the primary column
400
. By disabling or enabling a column select signal
250
each time an incoming address is received, the above device and method are inefficient. The device and method are also inefficient in terms of timing, since the column decoder
200
must wait for the output from the column address compare circuit
100
in order to proceed.
SUMMARY OF THE INVENTION
The present invention relates to a device and method for use in memory devices employing redundant rows and columns. The present invention provides a row or column latch device which includes an additional latch to latch the output of a row or column address compare circuit, such that a row or column select signal need not be disabled or enabled, to determine if a redundant row or column has been programmed for the incoming address, each time an incoming address is received. This reduces the circuitry in the row or column decoder because the circuitry to disable or enable the select signal is no longer needed. In addition, the device and method of the present invention do not require the row or column decoder to wait for the results of the row or column address compare circuit, thus increasing the speed of the memory device.
REFERENCES:
patent: 5410582 (1995-04-01), Sato
patent: 5548787 (1996-08-01), Okamura
patent: 5966333 (1999-10-01), Otani et al.
patent: 6144592 (2000-11-01), Kanda
patent: 6178532 (2001-01-01), Pierce et al.
Ingalls Charles L.
Vo Huy T.
Dickstein , Shapiro, Morin & Oshinsky, LLP
Dinh Son T.
Micro)n Technology, Inc.
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