Latched row decoder for a random access memory

Details Latched row decoder for a random access memory Latched row decoder for a random access memory

1995-06-07

1997-03-25

Dinh, Son T.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518905, 365200, 36523008, G11C 800

Patent

active

056151640

ABSTRACT:
A latched row decoder for a Random Access Memory (RAM). The Decoder includes a set-reset latch that is set when addressed and remains set until reset by a PRE signal; address select logic; a reset device; and gated word line drives. The latch, when set, enables four word line drivers that are driven individually depending on two row address bits. During test, latched decoders may be selected sequentially and not reset, leaving drivers enabled until a test is complete. Thus some or all word lines may be driven simultaneously during test. A RAM including the latched decoder of the present invention has a normal random access mode and at least 4 test modes. The test modes are: Long t.sub.RAS word line disturb mode; toggled word line disturb mode; transfer gate stress mode; and a stress test mode.

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patent: 5341341 (1994-08-01), Fukuzo
patent: 5511034 (1996-04-01), Hirata

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