Latched address multi-chunk write to EEPROM

Details Latched address multi-chunk write to EEPROM Latched address multi-chunk write to EEPROM

2000-08-21

2003-04-01

Thai, Tuan V. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C365S189050, C365S222000

Reexamination Certificate

active

06542956

ABSTRACT:

FIELD OF THE INVENTION
This invention relates in general to data write circuits for memory devices and in particular, to a multi-chunk data write circuit and method for concurrently writing more than one addressable chunk of data at a time to an electrically-erasable and programmable read-only memory (EEPROM).
BACKGROUND OF THE INVENTION
In a conventional EEPROM, data is written one addressable data chunk at a time. Accordingly, a multi-chunk write operation includes several repetitions of providing an address and a data chunk to be written at that address, then programming and verifying the programming of the data chunk into that address. Since the time for programming and verifying the programming of each chunk of data generally far exceeds the time required for providing the address and the data for each chunk of data, such multi-chunk write operations in a conventional EEPROM tend to be very slow.
OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a multi-chunk write circuit and method for performing multi-chunk write operations to an EEPROM in a significantly faster manner than conventional EEPROM write circuits and methods.
This and additional objects are accomplished by the various aspects of the present invention, wherein briefly stated, one aspect is a multi-chunk write circuit which concurrently writes and verifies the writing of multiple chunks of data at a time into an EEPROM, thereby performing multi-chunk write operations significantly faster than conventional EEPROM write circuits which sequentially write a chunk of data at a time into an EEPROM.
Another aspect is a circuit for concurrently writing data into selected ones of a plurality of subarrays of EEPROM cells. Included in the circuit are means for storing a plurality of addresses indicative of locations in the plurality of subarrays of EEPROM cells; a plurality of data registers coupled to the plurality of subarrays of EEPROM cells; and means for sequentially storing addresses into the storing means and corresponding data into the plurality of data registers, and concurrently writing the data stored in the plurality of data registers into the locations in the plurality of subarrays corresponding to the stored addresses.
In another aspect, a method of concurrently writing a plurality of data chunks into an EEPROM, comprises the steps of: sequentially storing the plurality of data chunks into a plurality of data storage means respectively coupled to corresponding subarrays of the EEPROM; providing row and column select signals to row and column decoder means coupled to the corresponding subarrays of the EEPROM; and concurrently writing the plurality of data chunks stored in the plurality of data storage means into the corresponding subarrays of the EEPROM as indicated by the row and column select signals.
Additional objects, features and advantages of the various aspects of the present invention will become apparent from the following description of its preferred embodiment, which description should be taken in conjunction with the accompanying drawings.


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