Latched address multi-chunk write to EEPROM

Details Latched address multi-chunk write to EEPROM Latched address multi-chunk write to EEPROM

2011-02-15

2011-02-15

Thai, Tuan V. (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S100000, C711S102000, C711S154000

Reexamination Certificate

active

07890694

ABSTRACT:
An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.

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