Electronic digital logic circuitry – Reliability – Fail-safe
Reexamination Certificate
2008-04-08
2008-04-08
Chang, Daniel (Department: 2819)
Electronic digital logic circuitry
Reliability
Fail-safe
C326S044000, C327S534000, C327S536000, C327S537000
Reexamination Certificate
active
07355437
ABSTRACT:
An integrated circuit such as a programmable logic device integrated circuit is provided that contains body-biased metal-oxide-semiconductor transistors and latch-up prevention circuitry to prevent latch-up from occurring in metal-oxide-semiconductor transistors. Body bias signals can be received from an external source or generated internally. Body bias paths are used to distribute the body bias signals to the body terminals of the metal-oxide-semiconductor transistors. The latch-up prevention circuitry may include active n-channel and p-channel metal-oxide-semiconductor transistor latch-up prevention circuitry. The latch-up prevention circuitry monitors the states of power supply signals to determine whether a potential latch-up condition is present. If the latch-up prevention circuitry determines that a core logic power supply signal and ground power supply have become valid while a body bias signal is not valid, a body bias path can be clamped at a safe voltage to prevent latch-up from occurring in the metal-oxide-semiconductor transistors.
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Altera Corporation
Chang Daniel
Treyz G. Victor
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