Latch type sense amplifier having a negative feedback device

Details Latch type sense amplifier having a negative feedback device Latch type sense amplifier having a negative feedback device

1997-07-28

1999-03-16

Nelms, David

Static information storage and retrieval

Read/write circuit

Differential sensing

36518905, 365205, G11C 702

Patent

active

058838465

ABSTRACT:
A latch type sense amplifier having negative feedback means for use in a memory device includes a first switching unit which is turned on/off by an enable signal and initializes a system operation at a turn-on operation; a second switching unit which is turned on/off according to the voltage state of the data on two data lines at the turn-on operation of the first switching unit and performs a system initial operation; a third switching unit which is turned on by a precharge signal and initializes two output signals; a latch unit for latching the data input via the second switching unit according to the operation of the third switching unit and outputting the latched data to two data output units; and a feedback switching unit which is connected to the data output units of the latch unit and the data lines, is turned on/off according to the voltage state of the other data output unit and pulls-up the voltage difference of the bit line connected to corresponding data line by the voltage on corresponding data output terminal at an on operation.

REFERENCES:
patent: 5278790 (1994-01-01), Kanabara
patent: 5457657 (1995-10-01), Suh
patent: 5502680 (1996-03-01), Du et al.
patent: 5615161 (1997-03-01), Mu
Tsuguo Kobayashi et al.; "A Current-mode Latch Sense Amplifier and a Static Power Saving Input Buffer for Low-power Architecture;" 1992 Symposium on VLSI Circuits Digest of Technical Papers; pp. 28-29.
Fumio Miyaji et al.; "A 25-ns 4-Mbit CMOS SRAM with Dynamic Bit-Line Loads;" 1989 IEEE.

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