Latch type level shift circuit

Details Latch type level shift circuit Latch type level shift circuit

1999-12-22

2001-12-25

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Amplitude control

C327S057000, C327S225000, C365S189110, C365S228000, C365S230060, C365S230080, C326S080000

Reexamination Certificate

active

06333662

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a latch type level shift circuit and more particularly to a latch type level shift circuit used for a row decode circuit.
Recently, a flash EEPROM has received much attention as a nonvolatile semiconductor memory which can be integrated with high integration density. The memory has a feature that data items of memory cells can be instantaneously erased in a lump in the unit of block.
As the flash EEPROM, a NOR type, NAND type and the like are known. In any type of flash EEPROM, the cell structure may be generally formed of a stack type by stacking a plurality of polysilicon layers to form a floating gate electrode and control gate electrode.
FIG. 1
shows the main portion of a NOR type flash EEPROM as an example of the flash EEPROM.
A memory cell array
11
has a plurality of memory cells MC arranged in an array form. For example, the memory cell MC has a stack type cell structure as shown in
FIG. 2. A
plurality of word lines WL
0
, WL
1
, . . . , WLn extending in the row direction and a plurality of bit lines BL
0
, BL
1
, . . . , BLm extending in the column direction are arranged on the memory cell array
11
.
For example, a plurality of row decode circuits RD•
0
, R•
1
, . . . , RD•n are respectively provided for the plurality of word lines WL
0
, WL
1
, . . . , WLn. One end of the word line WLi (i is 0, 1, . . . , n) is connected to the corresponding row decode circuit RD•i.
A column selecting circuit
12
is connected to the plurality of bit lines BL
0
, BL
1
, . . . , BLm and selects one of the columns based on an output signal from a column decode circuit CD. The bit line on the selected column is electrically connected to an input register
13
or sense amplifier
14
. An input/output buffer
15
is provided to transfer data between the interior and the exterior of the memory chip.
A row address signal is input to the plurality of row decode circuits RD•
0
, RD•
1
, . . . , RD•n via an address register
16
. A column address signal is input to the column decode circuit CD via the address register
16
.
FIG. 3
shows one example of the row decode circuit and a control circuit therefore.
The row decode circuit RD•i is constructed by a row decoder
29
and latch type level shift circuit
30
.
The row address signal is input to the row decoder
29
via the address register
16
. The row decoder
29
supplies decode signals Ai, {overscore (Ai)} indicating the result of decoding of the row address signal to the latch type level shift circuit
30
. When the row containing the word line WLi is selected, the decode signal Ai is set to “H” and the decode signal {overscore (Ai)} is set to “L”.
A write enable signal {overscore (WE)}, chip enable signal {overscore (CE)} and command signal are input to a mode select circuit
23
. The mode select circuit
23
supplies erase signals ERASE*, {overscore (ERASE*)} to the latch type level shift circuit
30
.
A potential generating circuit (booster or charge pump circuit)
24
outputs VROW (positive potential or ground potential). VROW is supplied to the latch type level shift circuit
30
via a regulator
25
. A potential generating circuit (booster or charge pump circuit)
26
outputs VBB (ground potential or negative potential). VBB is supplied to the latch type level shift circuit
30
via a regulator
27
.
A negative potential detecting circuit
28
detects the value of VBB, sets VBBDET to “H” when VBB is lower than a preset value (for example, −4V) and sets VBBDET to “L” when VBB is higher than the preset value. Further, it sets {overscore (VBBDET)} to the same value as VBB when VBB is set at a negative potential and sets {overscore (VBBDET)} to “H” when VBB is set at a ground potential.
FIG. 4
shows one example of the row decoder.
The row decoder includes a NAND circuit
17
supplied with a row address signal and an inverter circuit
18
. The NAND circuit
17
outputs a decode signal {overscore (Ai)} and the inverter circuit
18
outputs a decode signal Ai.
FIG. 5
shows one example of the latch type level shift circuit
30
.
A latch circuit constructed by inverter circuits INV
1
, INV
2
is connected between nodes A and B. The node B is connected to the input terminal of an inverter circuit INV
4
. An output signal OUT of the inverter circuit INV
4
is supplied to the word line WLi. A signal VBBDET is input to an inverter circuit INV
3
and an internal power supply potential VROW′ is output from the inverter circuit INV
3
. The internal power supply potentials VROW′, VBB are supplied to the inverter circuits INV
1
, INV
2
, INV
4
.
N-channel MOS transistors MN
1
, MN
3
are serially connected between the node A and a ground node VSS and N-channel MOS transistors MN
2
, MN
4
are serially connected between the node B and the ground node VSS. The gates of the MOS transistors MN
3
, MN
4
are supplied with a signal {overscore (VBBDET)}.
The signal {overscore (VBBDET)} is set to the same value as VBB when VBB is set at a negative potential and is set to “H” when VBB is set at the ground potential.
The gate of the MOS transistor MN
1
is supplied with an output signal VAB of a NOR circuit
21
and the gate of the MOS transistor MN
2
is supplied with a signal VA obtained by inverting the output signal VAB of the NOR circuit
21
by use of an inverter circuit
22
. Output signals of AND circuits
19
,
20
are input to the NOR circuit
21
. The AND circuit
19
is supplied with the decode signal Ai and erase signal {overscore (ERASE*)} and the AND circuit
20
is supplied with the decode signal {overscore (Ai)} and erase signal ERASE*.
In the flash EEPROM with the above construction, generally, the selected word line is applied with a positive or negative high potential. For example, at the time of program (the operation for injecting electrons into the floating gate electrode), a potential of approx. 9V is applied to the selected word line, and at the time of erase (the operation for extracting electrons from the floating gate electrode), a potential of approx. −9V is applied to the selected word line. In this case, 0V is applied to the non-selected word lines.
In the present example, the level shift circuit is formed as a latch type. Further, in order to prevent positive and negative high potentials from being simultaneously applied to the inverter circuit, the power supply potential applied to the inverter circuit is changed.
For example, when VROW′ is output to the selected word line, VROW′ (for example, 9V) and VBB (for example, 0V) are applied to the inverter circuit, and when VBB is applied to the selected word line, VROW′ (for example, 0V) and VBB (for example, −9V) are applied to the inverter circuit.
Next, the operation of the flash EEPROM of
FIGS. 1
to
5
is explained.
Program Operation (Pre-Program Operation)
First, ERASE* is set to “L”, {overscore (ERASE*)} is set to “H”, VROW is set to 9V and VBB is set to 0V. Since VBB is set at 0V, the negative potential detecting circuit outputs VBBDET of “L”.
Since all of the row address signals are set at “H” in the row decoder RD•i of the selected row, Ai is set to “H” and {overscore (Ai)} is set to “L”. At this time, the output signal VAB of the NOR circuit
21
is set to “L” and the output signal VA of the inverter circuit
22
is set to “H”. As a result, the MOS transistor MN
1
is set into the OFF state and the MOS transistor MN
2
is set into the ON state.
Since {overscore (VBBDET)} is set at “H”, the MOS transistors MN
3
, MN
4
are set in the ON state. Therefore, the ground potential Vss is transmitted to the node B of the latch circuit. That is, a potential VLB of the node B of the latch circuit is set to VBB or “L (=0V)”, a potential VLA of the node A is set to VROW′ or “H (=9V)”, and the state of the latch circuit is determined. Since the potential VLB of the node B is set at “L”, the output signal OUT of the inverter circuit INV
4
is set to “H (=9V)”.
When VBBDET is set at “L”, the internal powe

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