Latch structure, frequency divider, and methods for...

Details Latch structure, frequency divider, and methods for... Latch structure, frequency divider, and methods for...

2009-09-02

2011-11-15

Le, Don (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C326S093000

Reexamination Certificate

active

08058901

ABSTRACT:
A latch includes three circuits. The first circuit drives a first output (QB) to a first level when a first input (D) and a first clock phase (CK) are both low, to a second level when D and CK are both high, and provides high impedance (HI-Z) when different logic levels are applied to D and CK. The second circuit drives a second output (Q) to the first level when a third input (DB) and a complimentary clock phase (CKB) are both low, to the second level when DB and CKB are both high, and provides HI-Z when different logic levels are applied to DB and CKB. The third circuit maintains voltages of Q and QB when the first and second circuits provide HI-Z at Q and QB. Odd-number dividers constructed with such latches produce 50% duty cycle operation without restricting output pulse widths to integer multiples of input periods.

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