Electronic digital logic circuitry – Interface – Current driving
Reexamination Certificate
1999-07-28
2002-06-18
Phan, Trong (Department: 2818)
Electronic digital logic circuitry
Interface
Current driving
C326S083000
Reexamination Certificate
active
06407580
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a sense amplifier circuit, and more particularly to a latch sense amplifier circuit to be used in a semiconductor memory device.
Recently, due to increases in the requirement for improvements in high speed performances of semiconductor devices and for possible reduction in power consumption of semiconductor devices, semiconductor memory devices are also requited to have improved high speed performance and reduced power consumption.
There are known different types of the sense amplifier circuits, wherein a latch type sense amplifier circuit is advantageous for zero stand-by current consumption and also is capable of high speed amplification of a small slight potential difference generated by memory cells. This latch sense amplifier circuit is, however, disadvantageous in that any malfunction is likely to appear on the sense amplifier circuit because a flip-flop in a latch circuit performs an amplification by a slight potential difference of several tens of millivolts. In order to avoid any malfunction of the sense amplifier circuit, a sufficient margin for potential difference is needed.
FIG. 1
is a circuit diagram illustrative of a conventional latch sense amplifier circuit. The conventional latch sense amplifier circuit comprises a flip-flop
1
, a transfer gate
2
, a next stage buffer
3
A and an output circuit
4
. The flip-flop
1
performs a high speed amplification of data from memory cells up to a level defined to be a difference of a high power voltage Vcc from a ground potential GND so as to output paired complementary signals therefrom. The transfer gate
2
is connected between the flip-flop
1
and the read buses RBT and RBB, so that the transfer gate
2
disconnects the flip-flop
1
from read buses RBT and RBB for latching data from the memory cells. The next stage buffer
3
A is connected to an output side of the flip-flop
1
for receiving the amplified complementary signals from the flip-flop
1
. The output circuit
4
are connected to the next stage buffer
3
A for receiving output from the next stage buffer
3
A to output the amplified memory cell data.
The flip-flop
1
has a parallel connection of first and second inverters INV
1
and INV
2
between both nodes SAT and SAB. Directions of the first and second inverters INV
1
and INV
2
are opposite to each other to form a closed loop. Namely, an output side of the first inverter INV
1
is connected to an input side of the second inverter INV
2
and an output side of the second inverter INV
2
is connected to an input side of the first inverter INV
1
. Power terminals of the first and second inverters INV
1
and INV
2
are supplied with a second sense amplifier activation signal SE
2
If the second sense amplifier activation signal SE
2
is low level or inactivated level, then the flip-flop
1
is inactivated to be inoperable. Ground terminals of the first and second inverters INV
1
and INV
2
are connected through an n-channel MOS field effect transistor Q
1
to a ground line GND. The n-channel MOS field effect transistor Q
1
has a gate receiving a first sense amplifier activation signal SE
1
. If the fist sense amplifier activation signal SE
1
is low level, then the nodes SAT and SAB awe kept to be the high power voltage level Vcc.
The transfer gate
2
has first and second p-channel MOS field effect transistors Q
2
and Q
3
which have gates receiving the second sense amplifier activation signal SE
2
. The first p-channel MOS field effect transistor Q
2
is connected in series between the read bus RBT and the node SAT. The second p-channel MOS field effect transistor Q
3
is connected in series between the read bus RBB and the node SAB which are connected to the opposite sides of the closed loops. If the second sense amplifier activation signal SE
2
is high level, then the flip-flop
1
is disconnected from the read buses RBT and RBB.
The next stage buffer
3
A and the output circuit
4
have well known circuit configurations as disclosed in Japanese laid-open patent publications Nos. 3-41820 and 4-109494.
The next stage buffer
3
A has a pair of first and second NOR gates NOR
1
and NOR
2
. One input of each of the first and second NOR gates NOR
1
and NOR
2
is connected to an output side of a third inverter INV
3
. This third inverter INV
3
has an input side receiving the first sense amplifier activation signal SE
1
. Namely, the inverted first sense amplifier activation signal SE
1
-bar is applied to one input of each of the first and second NOR gates NOR
1
and NOR
2
. Other terminal of the first NOR gate NOR
1
is connected to the node SAT. Other terminal of the second NOR gate NOR
2
is connected to the node SAB.
The output circuit
4
has a fourth inverter INV
4
and a series connection of a third p-channel MOS field effect transistor Q
4
and a second n-channel MOS field effect transistor Q
5
between a high voltage line and a ground line. The third p-channel MOS field effect transistor Q
4
is connected to the high voltage line. The second n-channel MOS field effect transistor Q
5
is connected to the ground line. The fourth inverter INV
4
has an input side connected to an output side of the second NOR gate NOR
2
. The third p-channel MOS field effect transistor Q
4
has a gate connected to the output of the fourth inverter INV
4
. The second n-channel MOS field effect transistor Q
5
has a gate connected to the output of the first NOR gate NOR
1
. An output terminal of the latch sense amplifier cirucit is connected to an intermediate node between the third p-channel MOS field effect transistor Q
4
and the second n-channel MOS field effect transistor Q
5
. An output signal SAOUT is outputted from the output terminal.
The following descriptions will focus on operations of the above described latch sense amplifier circuit. A memory cell is selected in data read operation. A small or slight potential difference is generated by the memory cell. This small or slight potential difference is transmitted to the sense amplifier circuit through digit lines not illustrated, read buses RBT and RBB which provide interconnections between the digit lines and the sense amplifier circuit. The small or slight potential difference is further transmitted through the transfer gate
2
. The small or slight potential difference appears across the nodes SAT and SAB. Thus, the small or slight potential difference appears across the opposite sides of the closed loop of the first and second inverters INV
1
and INV
2
.
If the first sense amplifier activation signal SE
1
becomes high level, then the first n-channel MOS field effect transistor Q
1
turns ON, whereby the small or slight potential difference gradually increases and also the potentials of the nodes SAT and SAB drop to an intermediate level between the high voltage level Vcc and the ground level. When a sufficient voltage for amplification is generated across the nodes SAT and SAB, the second sense amplifier activation signal SE
2
becomes high level, whereby a power is supplied to the flip-flop
1
and the potential of the node SAT rises up to the high voltage level whilst the potential of the node SAB drops to the ground level. Namely, the potential difference between the nodes SAT and SAB is increased to the potential difference between the high voltage level Vcc and the ground level GND. Since the first sense amplifier activation signal SE
1
has been activated in high level, both the first and second NOR gates NOR
1
and NOR
2
in the next stage buffer
3
are activated, so that data signals on the nodes SAT and SAB are transmitted to the output circuit
4
, whereby data read from the selected memory cells are output from the output terminal as an output signal SAOUT.
FIG. 2
is a circuit diagram illustrative of each of first and second NOR gates NOR
1
and NOR
2
in the next stage buffer
3
A in the latch sense amplifier circuit of FIG.
1
. Each of the first and second NOR gates NOR
1
and NOR
2
in the next stage buffer has the normal circuit configuration. In this case, the follow
Matsui Yuuji
Takahashi Hiroyuki
NEC Corporation
Phan Trong
Sughrue Mion Zinn Macpeak & Seas, PLLC
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