Latch modeling technique for formal verification

Details Latch modeling technique for formal verification Latch modeling technique for formal verification

2007-08-07

2007-08-07

Dinh, Paul (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

11051109

ABSTRACT:
A method for formal verification includes a latch remodeling process to reduce computational requirements for clock modeling. Latches that exhibit flip flop-like output behavior in a synthesized layout of sequential logic are identified and replaced with flip flops to generate a remodeled layout. This latch replacement can be performed using rules that filter out latches that do not exhibit flip flop-like output behavior. Clock modeling is then performed on the remodeled layout. Because the remodeled layout contains fewer latches than the original synthesized layout, the computational expense and time required for clock modeling (and hence, formal verification) on the remodeled layout can be significantly reduced over the requirements for clock modeling (and formal verification) on the original synthesized layout.

REFERENCES:
patent: 5539330 (1996-07-01), McDermid
patent: 5886904 (1999-03-01), Dai et al.
patent: 6587997 (2003-07-01), Chen et al.
patent: 2003/0120985 (2003-06-01), Slobodnik et al.

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