Latch interface for self-reset logic

Details Latch interface for self-reset logic Latch interface for self-reset logic

1994-08-18

1996-01-30

Westin, Edward P.

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Field-effect transistor

326 98, 327142, H03K 190948

Patent

active

054883199

ABSTRACT:
A latch, connected between an input self-reset dynamic MOS logic circuit and an output self-reset dynamic MOS logic circuit, is provided with clocked interface circuitry to assure proper latching of the state of the input logic in the latch and provides a pulsed output to the output logic circuit. Circuitry is provided to control the self-reset operation of the input logic circuit such that the reset does not occur until a predetermined period of time after the leading edge of the clock pulse latching the state of the input self-reset circuit in the latch. The output of the latch is gated from the latch to the output self-reset circuit under the control of a chopper circuit. The chopper circuit provides a control pulse to gate the state of the latch to the output self-reset circuit a predetermined period of time after the data has been latched. The control pulse has a duration sufficient to assure that the state of the latch is registered in the output self-reset logic.

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