Latch clustering for power optimization

Details Latch clustering for power optimization Latch clustering for power optimization

2000-11-15

2003-08-19

Siek, Vuthe (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06609228

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuit design and more particularly to a system and method that clusters latches in integrated circuits to reduce power consumption.
2. Description of the Related Art
Clocks consume a large portion of the power in integrated circuit chips since they switch more frequently than other devices. The dynamic power consumption (the dominant portion for CMOS circuits) and the “crossover” power (due to transient DC paths through static CMOS circuits when both pull-up and pull-down devices are active) are both proportional to switching frequency. Generally, dynamic power consumption of a net equals one-half the capacitance multiplied by the voltage squared and the net switching frequency. This is reflected as (½C)V
2
F, where C is capacitance, V is voltage and F is net switching frequency. Reducing the clock net wiring will reduce capacitance and, therefore, reduce chip power consumption.
Most existing clock optimization methods operate after the circuits on a chip have been positioned and assume a fixed placement for the latches being driven by the clock. These methods alter the connections of clock nets to latches, the number, power level, connections, and placement of clock tree elements (e.g., buffers, clock gates, and clock splitters), and the routing and width of the clock nets. After or during clock optimization, some adjustments are made to the placement to accommodate the clock tree changes.
Therefore, there is a need for a system and method of clustering clock devices that decreases power consumption of the overall circuit.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements, identifying clusters of the clock feeding circuits (each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected), changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster, and adjusting positions of the clock feeding circuits within design constraints to further reduce the lengths of the wires.
Adjusting the positions of the clock feeding circuits includes moving the clock feeding circuits toward the clock signal supply device of each cluster to a point where a first force pulling each clock feeding circuit toward the clock signal supply device equals a second force pulling the clock feeding circuit toward an original clock feeding circuit location. The first and second forces are derivatives of cost function components. In addition, the step of identifying the clusters includes identifying subclusters within the clusters, the method further includes moving the clock feeding circuits toward centroids of the subclusters. Adjusting the positions also includes moving each of the subclusters as a group without changing relative positions of the clock feeding circuits within the subclusters, moving logic devices to minimize a cost function, and moving existing circuits to accommodate for the adjusting to reduce local wiring congestion.
It is a further embodiment the present invention provides a method of clock optimization that including creating an initial placement of clock feeding circuits according to clock signal requirements, identifying clusters of the clock feeding circuits (wherein each cluster includes a distinct clock signal supply device to which each clock feeding circuit within the cluster is connected), and changing pin connections between the clock feeding circuits and clock signal supply devices to switch selected ones of the clock feeding circuits to different clusters to reduce lengths of wires between the clock feeding circuits and the clock signal supply devices within each cluster. The pin connections are changed so as to minimize a cost function associated with moving the clock feeding circuits from an original clock feeding circuit location.


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IBM Technical Disclosure Bulletin, Method for Optimizing Clock Trees on VLSI Chips, Jan. 1991, pp. 288-291.

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