Latch circuit with state-walk logic

Details Latch circuit with state-walk logic Latch circuit with state-walk logic

1995-10-26

1997-03-25

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

326 26, 327198, 36523008, H03K 19096

Patent

active

056148461

ABSTRACT:
A latch circuit employs state-walk logic that makes the transition from "set" to "latched" states without the need for multiple phases, critical timing or introduction of extra periods into any timings to account for worst case scenarios. The has particular application to row address receivers for dynamic random access memories (DRAMs) and, in its basic form, comprises a pair of identical receiver circuits of opposite logic state when off, with clock and data inputs and true and complementary outputs. The receivers are turned on by an activating clock signal. When the receivers are enabled, address data is evaluated as soon as it is received causing the latch to be set. This is the first step in the "state walk" of the latch. The outputs of the latch are fed back to turn off the receiver circuits completing the second step of the "state walk". The circuit now ignores any changes in the input address data, thus latching the input data.

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