Latch circuit and method with complementary clocking and level s

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307289, 307455, 307269, H03K 3289, H03K 329, H03K 19086, H03K 513

Patent

active

051720116

ABSTRACT:
Latch circuit and method which permit two-phase latches and flip-flops to be intermixed in a system having level sensitive scanning without critical clock requirements. The circuit includes a master latch having a normal data input and a scan data input, and a slave latch connected to the master latch. A differential pair of clock signals is applied to the latches in a complementary manner during a normal mode of operation to load data from the normal data input to the master latch and to transfer the normal data from the master latch to the slave latch, and two separate low frequency non-overlapping scan clock phases are applied to the latches during a level sensitive scanning mode to load data from the scan data input to the master latch and to transfer the scan data from the master latch to the slave latch.

REFERENCES:
patent: 4156819 (1979-05-01), Takahashi et al.
patent: 4689497 (1987-08-01), Umeki et al.
patent: 4733218 (1988-03-01), Traa
patent: 4777388 (1988-10-01), Widener
patent: 4825097 (1989-04-01), Bazil et al.
patent: 4975595 (1990-12-01), Roberts et al.

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