Latch circuit and deserializer circuit

Electronic digital logic circuitry – Function of and – or – nand – nor – or not

Reexamination Certificate

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Reexamination Certificate

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07629814

ABSTRACT:
A latch includes a precharging unit, a memory logic unit, an input amplifying unit, and a clock synchronization switch. The memory logic unit and the input amplifying unit are arranged in a same transistor level. Thus, the latch has three transistor levels. Further, a current supply150is connected to the memory logic unit to control a current flowing through the memory logic unit.

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