Latch circuit and arithmetic unit having the same

Details Latch circuit and arithmetic unit having the same Latch circuit and arithmetic unit having the same

1997-08-12

1999-11-02

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327200, 327201, H03K 3356

Patent

active

059778083

ABSTRACT:
A latch circuit receives complementary signals and consists of an nMOS transistor whose source is connected to an input terminal of the latch circuit and a series-connected circuit consisting of first and second pMOS transistors arranged between and connected to a drain terminal of the nMOS transistor and a high-potential power supply. The complementary signals are a first signal and a second signal that is an inversion of the first signal. Each of the signals has a pulse characteristic that rising time is longer than falling time. The latch circuit latches a quick fall by passing the first signal through the nMOS transistor. On the other hand, the latch circuit latches a slow rise by turning on the second pMOS transistor in response to a fall in the second signal.

REFERENCES:
patent: 5638018 (1997-06-01), Sharpe-Geisler
patent: 5825225 (1998-10-01), Sugisawa et al.
"FET Gated Data Latch Circuit" by Wong, IBM technical disclosure bulletin, vol. 24, No. 6, Nov. 1981.
"Fast Propogation Complementary Metal Oxide Semiconductor LSSD Latch", IBM technical disclosure bulletin, vol. 37, No. 10, Oct. 1994.

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