Laser link decoder for DRAM redundancy scheme

Static information storage and retrieval – Read/write circuit – Bad bit

Patent

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

365 96, 3652257, 36523003, 36523006, 3072021, 307219, 307441, 307449, 371 103, G11C 2900

Patent

active

052709760

ABSTRACT:
A decoder for a memory redundancy scheme is disclosed which allows replacement of a number of memory cell locations in connection with the state of a plurality of fuses.

REFERENCES:
patent: 4546455 (1985-10-01), Iwahashi et al.
patent: 4638466 (1987-01-01), Fukumoto
patent: 4724422 (1988-02-01), Golab
patent: 4922134 (1990-05-01), Hoffmann et al.
patent: 4985866 (1991-01-01), Nakaizumi
patent: 5058059 (1991-10-01), Matsuo et al.
patent: 5153880 (1992-10-01), Owen et al.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Laser link decoder for DRAM redundancy scheme does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Laser link decoder for DRAM redundancy scheme, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Laser link decoder for DRAM redundancy scheme will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-1711754

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.