Laser induced current for semiconductor defect detection

Details Laser induced current for semiconductor defect detection Laser induced current for semiconductor defect detection

1999-03-01

2001-01-23

Dang, Hung Xuan (Department: 2873)

Optics: measuring and testing

Inspection of flaws or impurities

Surface condition

C250S559400

Reexamination Certificate

active

06177989

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to inspection of integrated circuits, and more particularly to inspecting integrated circuits using laser-induced current.
BACKGROUND OF THE INVENTION
The semiconductor industry has seen tremendous advances in technology in recent years, permitting dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second) to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board.
Typically, dies contain a bonding pad which makes the electrical connection to the semiconductor package. To shorten the electrical path to the pad, the bonding pads were moved to the side of the die nearest the transistors and other circuit devices formed in the die. Connection to the package is made when the chip is flipped over and soldered. As a result, the dies are commonly called flip chips in the industry. Each bump on a pad connects to a corresponding package inner lead. The packages which result are lower profile and have lower electrical resistance and a shortened electrical path. The plurality of ball-shaped conductive bump contacts (usually solder, or other similar conductive material) are typically disposed in a rectangular array. The packages are occasionally referred to as “Ball Grid Array” (BGA) or “Area Grid Array” packages.
FIG. 1
is a cross-sectional view of an example BGA device
10
. The device
10
includes an integrated circuit
12
mounted upon a larger package substrate
14
. Substrate
14
includes two sets of bonding pads: a first set of bonding pads
16
on an upper surface adjacent to integrated circuit
12
and a second set of bonding pads
18
arranged in a two-dimensional array across an underside surface. Integrated circuit
12
includes a semiconductor substrate
20
having multiple electronic components formed within a circuit layer
22
upon a front side surface of semiconductor substrate
20
during wafer fabrication. The back side surface
23
remains exposed after the device
10
is formed. The electronic components are connected by electrically conductive interconnect lines to form an electronic circuit. Multiple I/O pads
24
are also formed within circuit layer
22
. I/O pads
24
are typically coated with solder to form solder bumps
26
.
The integrated circuit is attached to the package substrate using the controlled collapse chip connection method, which is also known as the C4® or flip-chip method. During the C4 mounting operation, solder bumps
26
are placed in physical contact with corresponding members of the first set of bonding pads
16
. Solder bumps
26
are then heated long enough for the solder to reflow. When the solder cools, I/O pads
24
of integrated circuit
12
are electrically and mechanically coupled to the corresponding members of the first set of bonding pads
16
of the package substrate. After integrated circuit
12
is attached to package substrate
14
, the region between integrated circuit
12
and package substrate
14
is filled with an under-fill material
28
to encapsulate the C4 connections and provide additional mechanical benefits.
Package substrate
14
includes one or more layers of signal lines that connect respective members of the first set of bonding pads
16
and the second set of bonding pads
18
. Members of the second set of bonding pads
18
function as device package terminals and are coated with solder, forming solder balls
30
on the underside surface of package substrate
14
. Solder balls
30
allow BGA device
10
to be surface mounted to an ordinary PCB. During PCB assembly, BGA device
10
is attached to the PCB by reflow of solder balls
30
just as the integrated circuit is attached to the package substrate.
The C4 mounting of integrated circuit
12
to package substrate
14
prevents physical access to circuit layer
22
for failure analysis and fault isolation. Thus, new approaches that are efficient and cost-effective are required.
One prior method for analyzing defects in a circuit includes the use of a photo-emission microscope to view a circuit which is powered. Defects within the powered circuit photo-emit, wherein the photo-emissions are recorded with a photo-emission microscope. A drawback to this approach is that the location of the defect must be in a high state prior to examination of a particular region with the photo-emission microscope to be observable. Therefore, an apparatus and method that provides fast and cost effective analysis of semiconductor circuits is desirable.
SUMMARY OF THE INVENTION
In one embodiment, a process is provided for analyzing an integrated circuit using laser induced current and photoemissions. A laser source is positioned to scan the integrated circuit with laser light and induce current in nodes of the circuit. Laser light reflected from the integrated circuit is filtered using a laser filter. Photo-emissions from the integrated circuit are detected with a photo-emission detector.
In another embodiment, a process is provided for analyzing an integrated circuit. The process comprises scanning the integrated circuit with a beam of laser light having sufficient energy to induce a current in nodes of the integrated circuit. The laser light reflected from the integrated circuit is filtered, and a photo-emission generated from the induced current is then detected.
In yet another embodiment, a process for analyzing an electronic circuit comprises scanning the back side surface with a beam of electromagnetic radiation, whereby current is induced in nodes of the circuit; and detecting a photo-emission from the substrate resulting from the induced current in the circuit.
An apparatus is provided for analyzing an electronic circuit formed upon a front side surface of a semiconductor structure having opposed front side and backside surfaces in another embodiment. The apparatus comprises means for producing a beam of laser light; means for scanning the back side surface of the semiconductor structure with the laser light, whereby the laser light induces a current in nodes of circuit; and means for detecting a photo-emission from semiconductor structure resulting from the induced current.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.


REFERENCES:
patent: 6091488 (2000-07-01), Bishop
Hornguchi, Koshi, Microscopic Optical Beam Induced Current Measurements and Their Applications,International Measurement and Test Conference, IMTC 1994, p. 693-699.
Komoda, Hirotaka and Shimizu, Katsusuke, Optical Beam Induced Current Techniques for Failure Analysis of Very Large Scale Integrated Circuits Devices,Jpn. J. Appl. Phys., vol. 33 (1994) p. 3393-3401.
Nishikawa, A., Odani, C., Miura, N, Novel Failure Analysis Technique “Light Induced State Transition (LIST” Method Using an OBIC System, 23rdInternational Symposium for Testing and Failure Analysis, 1997, p. 159-163.
Wilson, Tony and Pester, Paul D., An Analysis of the Photoinduced Current from a Finely Focused Light Beam in Planar p-n Junctions and Schottky-Barrier Diodes,IEEE Transactions on Electron Devices, vol. Ed-34, p. 1564-1570.

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