Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2008-04-01
2008-04-01
Bragdon, Reginald (Department: 2189)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C714S005110, C710S003000, C710S052000
Reexamination Certificate
active
11761970
ABSTRACT:
Double buffering of serial transfers is provided in order to allow for increased serial transfer rate without requiring increased internal processing speeds. A laser driver serial controller serially receives a word including address bits and data bits. During a write operation, the address bits are serially shifted into an address shift register of the laser driver, and the data bits are serially shifted into a data shift register of the laser driver. After the address bits and data bits are completely shifted into the respective address and data shift registers, the address bits and data bits are transferred in parallel to address and data holding registers of the laser driver. After the parallel transfers of the address bits and data bits from the address and data shift registers to the address and data holding registers, the address and data shift registers are available to serially receive additional address bits and data bits of an additional word.
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Int'l Search Report for PCT/US2004/013601, Jan. 20, 2005.
Perez Miguel Gabino
Rees Theodore D.
Smith D. Stuart
Bragdon Reginald
Elantec Semiconductor Inc.
Fliesler & Meyer LLP
Vo Thanh D.
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