Large scaled fault tolerant ATM switch and a self-routing...

Details Large scaled fault tolerant ATM switch and a self-routing... Large scaled fault tolerant ATM switch and a self-routing...

1998-06-30

2002-07-30

Marcelo, Melvin (Department: 2663)

Multiplex communications

Fault recovery

C370S217000

Reexamination Certificate

active

06426940

ABSTRACT:

CLAIM OF PRIORITY
This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application entitled A LARGE-SCALED ATM SWITCH WITH FAULT TOLERANT SCHEME AND A SELF-ROUTING METHOD IN A 2N×N MULTIPLEXING SWITCH earlier filed in the Korean Industrial Property Office on Jun. 30, 1997, and there duly assigned Serial No. 29587/1997 a copy of which is annexed hereto.
BACKGROUND OF THE INVENTION
1. Technical Field
The present invention relates to a large-scale fault tolerant asynchronous transfer mode (ATM) switch and a method for implementing a large-scale asynchronous transfer mode (ATM) switch.
2. Related Art
In general, packet-switching technologies are used to relay data traffic via an address contained within a packet. Asynchronous transfer mode (ATM) is one of a class of such packet-switching technologies. Asynchronous transfer mode (ATM) is a telecommunications technique defined by American National Standards Institute (ANSI) and International Telegraph and Telephone Consultative Committee (CCITT).
American National Standards Institute (ANSI) is a nonprofit organization formed in 1918 to coordinate private sector standards development in the United States. The International Telegraph and Telephone Consultative Committee (CCITT) is an international committee established to promote standards for the development of telephone, telegraph systems, and data networks and to create the environment for interworking between the networks of the different countries of the world.
There are different types of asynchronous transfer mode (ATM) switches. The term “switch fabric” refers to the method of data being switched from one node to another within a network. The term “cell” refers to a fixed-length unit of data traveling through the switch fabric. Cell switching breaks up data streams into small units that are independently routed through the switch. The routing occurs mostly in hardware through the switching fabric. The combination of cell switching and scaleable switching fabrics are key components of asynchronous transfer mode (ATM).
In the area of asynchronous transfer mode (ATM) data transfer, consider a conventional large-scaled N×N switch and a method for implementing a large-scaled N×N switch using a 2n×n multiplexing switch architecture and n×n output switch. Any type of switch is allowed for the n×n output switch, but 2n×n multiplexing switch is made up of output buffering type switches. The multiplexing switch selects just the cells to be transmitted to n output ports, considering the routing tag according to the position of each switch among 2n inputs and transmits the cells as output.
For implementing a large-scale N×N switch, 1+log
2
(N
) stages are required and each stage needs (N
) switches. The stages from the first stage to log
2
(N
) stage consist of a plurality of 2n×n multiplexing switches. The last stage consists of a plurality of n×n output switches. Therefore, (N
)×log
2
(N
) 2n×n multiplexing switches and (N
) n×n output switches are required to implement a large-scaled N×N switch.
As a result of simulation for implementing the conventional large-scale N×N switch as mentioned above, it is known that on the average, the buffer within the 2n×n multiplexing switch that is positioned closest to the n×n output switch, has the lost cells. In other words, the 2n×n multiplexing switch at s(log
2
(N
),k) has the lost cells. The earlier a stage is, the fewer cells the buffer has. So, it results in that the probability of occurrence of cell loss in the 2n×n multiplexing switch at the last stage becomes higher, but on the other hand the cell loss ratio at earlier stages becomes considerably lower.
In the 2n×n multiplexing switch, the cells on the equal conditions are outputted to the n output ports in view of each switch. However there is a problem in that if one of the n output ports had some problems, the cell loss would occur continuously.
A variety of ATM switches and related devices currently exist, as disclosed in U.S. Pat. No. 5,274,642 to Widjaja et al. entitled Output Buffered Packet Switch With A Flexible Buffer Management Scheme, U.S. Pat. No. 5,367,520 to Cordell entitled Method And System For Routing Cells In An ATM Switch, U.S. Pat. No. 5,305,319 to Sowell entitled FIFO For Coupling Asynchronous Channels, U.S. Pat. No. 5,414,703 to Sakaue et al. entitled Asynchronous Cell Switch, U.S. Pat. No. 5,467,347 to Petersen entitled Controlled Access ATM Switch, U.S. Pat. No. 5,493,566 to Ljungberg et al. entitled Flow Control System For Packet Switches, U.S. Pat. No. 5,557,621 to Nakano et al. entitled ATM Switch And Control Method Thereof, U.S. Pat. No. 5,166,926 to Cisneros et al. entitled Packet Address Look-Ahead Technique For Use In Implementing A High Speed Packet Switch, and U.S. Pat. No. 5,130,984 to Cisneros entitled Large Fault Tolerant Packet Switch Particularly Suited For Asynchronous Transfer Mode (ATM) Communication.
Even though a variety of ATM switches and related devices currently exist, I believe that there is a need for an enhanced ATM switch and a self-routing method in order to solve the aforementioned problem.
SUMMARY OF THE INVENTION
For solving the above problems, the present invention is intended to provide a large-scale fault tolerant asynchronous transfer mode (ATM) switch to considerably reduce the cell loss probability and a self-routing method in a 2n×n multiplexing switch to transmit cells more quickly.
A 2n×n multiplexing switch for a large-scaled fault tolerant ATM switch includes:
2n valid (VD) extracting part which generates a valid (VD) signal and is used to select a cell among the 2n cells inputted every cell period according to the routing tag and to store said cell to a first in first out (FIFO) buffer;
FIFO selecting part which selects the FIFO buffer for each cell selected by using the valid (VD) signal to be stored and transmits the cell to the corresponding FIFO buffer;
2n shared FIFO buffers storing the 2n cells transmitted through the FIFO selecting part;
outputting part transmitting the cells stored in the shared FIFO buffers to the output ports;
cell counting part counting the number of cells stored in the shared FIFO buffers by using the information transmitted from the FIFO selecting part and outputting part;
back-pressure signal generating part which generates the back-pressure signals by using the information from the cell counting part; and
fault detector monitoring the faults of input ports by inputting the 2n valid (VD) signals from the valid (VD) extracting part.
According to one embodiment of a 2n×n multiplexing switch for a large-scaled fault tolerant ATM switch, it is preferable that the FIFO selecting part further comprises:
FIFO address extracting part generating the address of the FIFO where the inputted cell is to be stored; and
Banyan routing network transmitting the cell to the shared FIFO buffers by using the data generated in the FIFO address extracting part.
According to one embodiment of a 2n×n multiplexing switch for a large-scaled fault tolerant ATM switch, it is preferable that the FIFO address extracting part further comprises:
2n adders such that one of 2n valid (VD) signals is inputted in an adder and the result of the operation is outputted to the just next stage of the adder; and
2n buffers inputting the output of the adder of the present stage among the 2n adders.
According to one embodiment of a 2n×n multiplexing switch for a large-scaled fault tolerant ATM switch, it is preferable that the outputting part further comprises:
read FIFO address (RFA) generator generating n read FIFO address (RFA) signals for selecting the FIFO number to be read;
FIFO read enable (FRE) generator generating 2n FIFO read enable (FRE) signals by using the read FIFO address (RFA) signal; and
output-cell multiplexing part transmitting n cells to the output ports among 2n cells read from the

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