Large scale mixed-signal integrated circuit design

Details Large scale mixed-signal integrated circuit design Large scale mixed-signal integrated circuit design

1998-03-02

2002-09-17

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000

Reexamination Certificate

active

06453445

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a method for shrinking an existing integrated circuit (IC) design containing analog and digital circuitry and to the fabrication of a resultant IC.
An IC containing both analog and digital circuitry is also defined herein, and in the appended claims, as a “mixed signal” IC. In certain applications, it is desirable and/or necessary to shrink the physical size of the circuitry present on an existing IC to make more chips on the same wafer and/or to enable more circuits to be placed on a chip. Also, reducing the size of a chip, normally increases its production yield. To meet the challenge of shorter cycle (turn-around) times in the fabrication of “shrunken” large scale ICs, it is desirable to re-use the physical design of existing ICs. Optically shrinking an IC design is a fast, effective method of reducing the size of a chip, thereby increasing the yield; where “optically shrinking” refers, generally, to a process of using a smaller size beam to manufacture the various masks levels needed to manufacture an IC.
Digital circuits respond favorably when shrunk optically. In addition to a chip size reduction, the operating characteristics of a digital circuit will often improve with a reduction in size. Digital circuits on a chip can be “optically” shrunk without requiring special treatment. In a digital circuit, speed and power consumption are the main design parameters. It can be shown that in a digital design, speed is directly proportional to Vdd/L
2
, where Vdd is the circuit's operating voltage, and L is the transistor channel length. When optically shrinking a digital design, the transistor channel length is reduced, thereby increasing the speed parameter. In addition, due to the decrease in the size of the components, including stray and switching capacitances, power consumption is generally reduced. The speed increase and power reduction are very desirable outcomes.
However, shrinking analog circuitry presents a special problem because many analog circuits, such as amplifiers and filters, can not be optically shrunk without adversely affecting critical circuit parameters. By way of example, in analog circuits there are several circuit parameters that a designer must be concerned with. For example, in the case of a differential operational amplifier, some of the most common parameters are gain bandwidth, power supply rejection ratio, common mode rejection ratio, offset and phase margin. These parameters are all influenced by transistor width and channel length and by circuit parasitics such as stray capacitances. Optically shrinking the circuits will change all of these parameters, and it is highly unlikely that all of the circuit parameters would result in an IC meeting the specifications or performing optimally. Therefore, in contrast to digital circuits, most analog circuits when subjected to a straightforward optical shrink will not perform satisfactorily or will fail.
Thus, a significant problem exists when it is desired to shrink a mixed signal IC, since “optically” shrinking the “analog” portion of the IC is not acceptable. As a result, where it is desirable to maintain the functionality and characteristics of the original circuit, it is not possible to shrink a “mixed signal” IC without providing special treatment for the analog portion of the circuit.
SUMMARY OF THE INVENTION
Applicants'invention is directed to a method for shrinking an existing mixed-signal IC such that the “shrunken” IC includes an analog portion whose components are similar in size to those of the original, existing IC and includes a digital portion whose components are smaller in size than those of the original IC. A method of shrinking an existing mixed signal IC, in accordance with the invention, includes the step of first enlarging (growing) the analog circuitry by a first ratio, followed by the step of recombining the enlarged analog circuitry with the existing digital circuitry and, then, optically shrinking the recombined analog and digital circuits by a second ratio.
In one embodiment of the invention, the first and second ratios are selected to ensure that the physical size of the digital circuitry is reduced while the size of the analog circuitry is substantially equal to that of the original, existing, IC. That is, the analog circuits are grown (enlarged) by a factor that will offset the subsequent optical shrink. As a result, the analog circuitry is essentially unchanged on silicon, while the digital circuitry will be smaller, thereby making the overall chip smaller. Therefore, in shrunken ICs embodying the invention, the devices forming the analog circuitry will have similar parameters and characteristics to those of the original IC design and the digital circuitry will generally operate faster and at lower power dissipation.
The enlargement of the analog circuitry and the subsequent shrinking of the combined analog (enlarged) and digital circuitry yields a much shorter cycle time (when migrating a mixed-signal chip to a smaller technology using an optical shrink process) than could be obtained if the analog circuitry were redesigned from scratch.
An existing (“original” or “source”) mixed signal IC, when shrunk in accordance with the invention, is used to produce an “object” or “shrunk” IC which includes analog circuits whose components are comparable in size to those of the original, existing, IC and digital circuitry which is shrunken by a predetermined ratio. Thus, in accordance with the invention an “object” mixed signal IC may be produced having analog circuitry which is comparable in size to that of the “original” analog circuitry and having digital circuitry whose size is a predetermined ratio of the “original” circuitry.


REFERENCES:
patent: 6263479 (2001-07-01), Tajima

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