Large scale integrated circuit having low internal operating vol

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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3072966, 3072968, 307260, 328 59, 328 63, H03K 301, H03K 501

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active

052548805

ABSTRACT:
Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.

REFERENCES:
patent: 3975648 (1976-08-01), Tobey, Jr. et al.
patent: 4100437 (1978-07-01), Hoff, Jr.
patent: 4454467 (1984-06-01), Sakaguchi
patent: 4477737 (1984-10-01), Ulmer et al.
patent: 4495425 (1985-01-01), McKenzie
patent: 4507572 (1985-03-01), Hashimoto et al.
patent: 4618815 (1986-10-01), Swanson
patent: 4675557 (1987-06-01), Huntington
patent: 4866303 (1989-09-01), Karai et al.
patent: 4902911 (1990-02-01), Hoshi
patent: 4950921 (1990-08-01), Takada
patent: 5079441 (1992-01-01), Scott
patent: 5140182 (1992-08-01), Ichimura
Vittoz, et al., "a Low-Voltage CMOS Bandage Reference", IEEE JSSC, V. SC-14, No. 3, Jun. 1979, pp. 573-577 (307/2968).
Itoh, et al., "FAM 18-6: An Experimental 1Mb DRAM with On-Chip Voltage Limiter", ISCC Digest of Technical Papers, Feb. 1984, pp. 282-283.
Takada, et al., "FAM 19.6: A 4Mb DRAM with Half Internal-Voltage Bitline Precharge", from ISSCC Digest of Technical Papers, Feb. 1986, pp. 270-271.
Furuyama, et al., "FAM 19.7: An Experimental 4MB CMOS DRAM", ISSCC Digest of Technical Papers, Feb. 1986, pp. 272-273.
Furuyama, et al., "a New On-Chip Voltage Converter for Submicrometer High-Density DRAM's", IEEE Journal of Solid State Circuits, V. SC-22, No. 2, No. 3, Jun. 1987, pp. 437-441.
Gray, et al., Analysis and Design of Analog Integrated Circuits, 2 ED., John Wiley and Sons, Inc., Chapter 9: "Frequency Response and Stability of Feedback Amplifiers."
Koyanagi, et al., "A 5-V Only 16-kbit Stacked-Capacitor MOS RAM", IEEE Journal of Solid State Circuits, V. SC-15, No. 4, Aug. 1980, pp. 661-666.
Shimohigashi, et al., "WAM 1.4: A 65ns DRAM with a Twisted Driveline Sense Amplifier", ISSCC Digest of Technical Papers, Feb. 1987, pp. 18-19.

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