Large scale integrated circuit having low internal operating vol

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3073968, G11C 1140, H03K 301

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active

051795396

ABSTRACT:
Practical structures of an ultra large scale semiconductor integrated (ULSI) circuit especially a dynamic random access memory of 16 M bits or more are involved. The ULSI circuit uses internal operating voltages and how to construct a reference voltage generating circuit and a voltage limiter circuit in the ULSI circuit is a matter of importance. The operation of the reference voltage generating circuit and voltage limiter circuit can be stabilized, characteristics of these circuits are improved, and layout of these circuits as applied to memory cell array, peripheral circuits and the like can be improved. Improved methods of testing these circuits are provided.

REFERENCES:
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patent: 4260909 (1981-04-01), Dumbri et al.
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Masahide Takada, et al., "FAM 19.6: a 4Mb DRAM with Half Internal-Voltage Bitline Precharge", from ISSCC Digest of Technical Papers, Feb. 1986, pp. 270-271.
Tohru Furuyama, et al., "FAM 19.7: An Experimental 4Mb CMOS DRAM", from ISSCC Digest of Technical Papers, Feb. 1986, pp. 272-273.
Tohru Furuyama, et al., "A New On-Chip Voltage Converter for Submicrometer High-Density DRAM's", from IEEE Journal of Solid-State Circuits, vol. SC-22, No. 3, Jun. 1987, pp. 437-441.
Paul R. Gray, et al., Analysis and Design of Analog Integrated Circuits, 2nd Ed., John Wiley and Sons, Inc., specifically, "Chapter 9: Frequency Response and Stability on Feedback Amplifiers".
Mitsumasa Koyanagi, et al., "A 5-V Only 16-kbit Stacked-Capacitor MOS RAM", from IEEE Journal of Solid-State Circuits, vol. SC-15, No. 4, Aug. 1980, pp. 661-666.
Katsuhiro Shimohigashi, et al., "WAM 1.4: A 65ns DRAM with a Twisted Driveline Sense Amplifier", from ISSCC Digest of Technical Papers, Feb. 1987, pp. 18-19.

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