Large scale integrable memory cell with a trench capacitor where

Details Large scale integrable memory cell with a trench capacitor where Large scale integrable memory cell with a trench capacitor where

1989-06-26

1990-02-27

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Capacitors

365182, 357 236, G11C 1124

Patent

active

049051938

ABSTRACT:
A large scale integrable memory cell including a field effect transistor lying at a bit line and further including a storage capacitor which is formed by the wall of a trench and a cooperating electrode. The active region of the storage cell which lies outside the trench is fashioned in the form of a strip. The end face forms one part of the trench edge and the remaining portion of the trench edge is surrounded by a field oxide region.

REFERENCES:
patent: 4641279 (1987-02-01), Kimura et al.
patent: 4751557 (1988-06-01), Sunami et al.
patent: 4751558 (1988-06-01), Kenney
patent: 4752819 (1988-06-01), Koyama
patent: 4761385 (1988-08-01), Pfiester
patent: 4763179 (1988-08-01), Tsubouchi et al.
patent: 4774556 (1988-09-01), Fujii et al.
patent: 4792834 (1988-12-01), Uchida
IBM Tech. Discl. Bull., vol. 30, No. 12, May 88, pp. 109-110, "Self-Aligned Polycide Bitline Structure" (by no author).
"An Experimental 4-Mbit CMOS Dram", IEEE Journal of Solid-State Circuits, vol. SC-21, No. 5, Oct. 1986, pp. 605-611.

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