Large-input-delay variation tolerant (LIDVT) receiver...

Details Large-input-delay variation tolerant (LIDVT) receiver... Large-input-delay variation tolerant (LIDVT) receiver...

2006-05-02

2006-05-02

Corrielus, Jean (Department: 2637)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S373000, C375S375000, C375S376000

Reexamination Certificate

active

07039144

ABSTRACT:
The present invention discloses a multiple-stage FIFO mechanism capable of receiving data signals correctly. The circuit includes a write-enable pulse sequencer for sequentially generating a plurality of write-enable signals. An N-stage FIFO sequentially stores an input data and outputs the input data. An output stage selector sequentially generates a control signal. And a multiplexer selectively outputs the input data from the N-stage FIFO.

REFERENCES:
patent: 5272729 (1993-12-01), Bechade et al.
patent: 6366529 (2002-04-01), Williams et al.
patent: 6711227 (2004-03-01), Kaylani et al.
patent: 2001/0055357 (2001-12-01), Chen

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