Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
2004-09-08
2008-10-07
Lebentritt, Michael S. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
C438S217000, C438S514000, C257SE21133, C257SE21413, C257SE21423
Reexamination Certificate
active
07432141
ABSTRACT:
A method is disclosed to form a large-grain, lightly p-doped polysilicon film suitable for use as a channel region in thin film transistors. The film is preferably deposited lightly in situ doped with boron atoms by an LPCVD method at temperatures sufficiently low that the film is amorphous as deposited. After deposition, such a film contains an advantageous balance of boron, which promotes crystallization, and hydrogen, which retards crystallization. The film is then preferably crystallized by a low-temperature anneal at, for example, about 560 degrees for about twelve hours. Alternatively, crystallization may occur during an oxidation step performed, for example at about 825 degrees for about sixty seconds. The oxidation step forms a gate oxide for a thin film transistor device, for example a tunneling oxide for a SONOS memory thin film transistor device.
REFERENCES:
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6162711 (2000-12-01), Ma et al.
patent: 6235563 (2001-05-01), Oka et al.
patent: 6403497 (2002-06-01), Oka et al.
patent: 6570184 (2003-05-01), Horikoshi et al.
patent: 6713371 (2004-03-01), Gu
patent: 6905963 (2005-06-01), Noda et al.
patent: 6956278 (2005-10-01), Herner
patent: 2002/0132452 (2002-09-01), Oka et al.
patent: 2004/0033648 (2004-02-01), Matsunaga et al.
patent: 2004/0046209 (2004-03-01), Sera et al.
patent: 2005/0072976 (2005-04-01), Cleeves et al.
Fan, C.L., et al.,“Fabrication of High Performance Low-Temperature Poly-Si Thin-Film Transistors Using a Modulated Process”,J. Electrochem.Soc., vol. 149, (2002),H93-H97.
Nam, K.S., et al.,“Thin-Film Transistors with Polycrystalline Silicon Prepared by a New Annealing Method”,Jpn. J. Appl. Phys. Part 1, vol. 32, (1993), 1908-1912.
Subramanian, V., et al.,“Controlled Two-Step Solid-Phase Crystallization for High-Performance Polysilicon TFTs”,IEEE Electron Device Letters, vol. 18, (1997), 378-381.
Subramanian, V., et al.,“High-Performance Germanium-Seeded Laterally Crystallized TFT's for Vertical Device Integration”,IEEE Transactions on Electron Devices, vol. 45, (1998), 1934-1939.
Subramanian, V., et al.,“Low-leakage Germanium-Seeded Laterally-Crystallized Single-Grain 100-nm TFT's for Vertical Integration Applications”,IEEE Electron Device Letters, vol. 20, (1999), 341-343.
Wang, H., et al.,“Super Thin-Film Transistor with SOI CMOS Performance Formed by a Novel Grain Enhancement Method”,IEEE Transaction on Electron Devices, vol. 47, (2000), 1580-1586.
Gu Shuo
Nallamothu Sucheta
Foley & Lardner LLP
Isaac Stanetta D
Lebentritt Michael S.
SanDisk 3D LLC
LandOfFree
Large-grain p-doped polysilicon films for use in thin film... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Large-grain p-doped polysilicon films for use in thin film..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Large-grain p-doped polysilicon films for use in thin film... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3988768