Large current capacity semiconductor device

Details Large current capacity semiconductor device Large current capacity semiconductor device

2002-12-26

2004-11-23

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S372000

Reexamination Certificate

active

06822298

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device, specifically to a charge pump device with large current capacity used for a power supply circuit. Performance of the charge pump device can be improved and a latch up can be prevented with this invention.
2. Description of the Related Art
Video equipment in recent years such as a camcorder, a digital still camera (DSC) and a mobile phone with DSC use CCDs (charge-coupled devices) to capture an image. A CCD drive circuit for driving the CCDs requires a power supply circuit that provides both positive and negative high voltages (over 10 volts) and a large current (several milliamperes). A switching regulator is used for that purpose today.
The switching regulator can generate a high voltage with high performance, i.e. with high power efficiency (output power/input power). However, it has a drawback to generate a harmonic noise when switching a current. Therefore, the power supply has to be used with a noise shield. In addition to that, it requires a coil as an external part.
Consequently, a Dickson charge pump device has come to attention as a power supply circuit for portable equipment described above. The Dickson charge pump device is described in detail in a technical journal “John F. Dickson ‘On-chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multiplier Technique’, IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.SC-11, No.3, pp.374-378, Jun. 1976”, for example.
FIG. 18
shows a circuit diagram of a four-stage Dickson charge pump device. Diodes D
1
-D
5
are connected in series. Each of coupling capacitors C
1
-C
4
is connected to each of connecting nodes between the diodes D
1
-D
5
. CL refers to an output capacitor. CLK and CLKB are input clock pulses having opposite phase to each other. The CLK and CLKB are inputted to a clock driver
51
. A numeral
52
refers to a current load. The clock driver
51
is provided with a power supply voltage Vdd. Herewith, an output amplitude of the clock pulses &PHgr;
1
and &PHgr;
2
outputted from the clock driver
51
becomes Vdd. The clock pulse &PHgr;
1
is fed to the capacitors C
2
and C
4
, while the clock pulse &PHgr;
2
is fed to the capacitors C
1
and C
3
.
In a stable state, in which a constant current Iout flows out, an input current to the charge pump device is a sum of a current from an input voltage Vin and a current provided from the clock driver. These currents are as described below, disregarding charging/discharging currents to/from stray capacitors. During a period of &PHgr;
1
=High and &PHgr;
2
=Low, an average current of 2 Iout flows through each of paths in directions depicted in the figure as solid line arrows.
During a period of &PHgr;
1
=Low and &PHgr;
2
=High, an average current of 2 Iout flows through each of paths in directions depicted in the figure as dashed line arrows. An average current of each of these currents over a clock cycle is Iout. A boosted voltage from the charge pump device in the stable state is expressed by an equation (1),
V
out=
V
in−
Vd+n
(
V&phgr;′−V
1
−Vd
)  (1)
where V&phgr;′ refers to an amplitude of a voltage at each of the connecting nodes induced through the coupling capacitor by a change in the clock pulse; V
1
denotes a voltage drop due to the output current Iout; Vin denotes the input voltage, which is usually set at Vdd in positive voltage boosting and at 0V in negative voltage boosting; Vd refers to a forward bias diode voltage; and n denotes a number of stages of pumping. Furthermore, V
1
and V&phgr;′ are expressed by following equations,
V
1
=I
out/(
f
(
C+Cs
))=(2
I
out
T
/2)/(
C+Cs
)  (2)
V&phgr;′=V&phgr;C
/(
C+Cs
)  (3)
where C
1
-C
4
denote clock coupling capacitances; Cs denotes a stray capacitance at each of the connecting nodes; V&phgr; denotes the amplitude of the clock pulses; f denotes a frequency of the clock pulses; and T denotes a clock period of the clock pulses. Power efficiency of the charge pump device is expressed by following equation, disregarding charging/discharging currents from/to the clock driver to/from the stray capacitors and assuming Vin=Vdd.
&eegr;=V
out
I
out/((
n
+1)
Vdd I
out)=
V
out/((
n
+1)
Vdd
)  (4)
In this way, the charge pump device boosts the voltage by successively transferring electric charge to a next stage using a diode as a charge transfer device. However, an MOS transistor is easier than a PN junction diode to implement in a semiconductor integrated circuit because of compatibility of the manufacturing process.
For this reason, using MOS transistors as the charge transfer devices in place of the diodes D
1
-D
5
has been proposed. In this case, Vd in the equation (1) is replaced with Vth representing a threshold voltage of the MOS transistor.
The inventors have investigated applying the charge pump device to a power supply circuit. The inventors have found following issues.
The first issue is to reduce ON resistance of a charge transfer MOS transistor, so that the charge pump circuit can provide a high voltage (over 10V) and a large current (several milliamperes) required to the power supply circuit.
The second issue is to prevent a latch up, which often happens to a high current charge pump device. Especially, there has been a problem with a large current charge pump device to cause a latch up at the beginning of the operation. The mechanism of the latch up based on the investigation made by the inventors will be described hereinafter.
FIG. 20
is a cross-sectional view showing a charge pump device implemented in a CMOS structure.
The structure shown in the cross-sectional view corresponds to that of the charge transfer MOS transistors M
2
and M
3
shown in FIG.
19
. Separate P-type well regions
31
and
32
are formed in an N-type well region
20
formed in a surface of a P-type semiconductor substrate
10
. And the charge transfer MOS transistor M
2
is formed in the P-type well region
31
. The charge transfer MOS transistor M
3
is formed in the P-type well region
32
.
Detailed explanation on the charge transfer MOS transistor M
2
formed in the P-type well region
31
is given hereinafter. A drain layer D and a source layer S, both of which are N+-type, are formed in the surface of the P-type well region
31
. P+ layers
41
, having higher impurity concentration than the P-type well region
31
, are formed in the P-type well region
31
. The drain layer D and the P+ layers
41
are electrically connected with an aluminum interconnection or the like.
Since the drain D of the charge transfer transistor M
2
and the P-type well region
31
, in which the charge transfer MOS transistor M
2
is formed, are electrically connected through low resistance, an increase in a threshold voltage Vth of the charge transfer transistor M
2
due to a back gate effect is surely prevented. The charge transfer transistor M
3
formed in the P-type well region
32
is structured similarly. Also, other charge transfer transistors M
1
, M
4
and M
5
, which are not shown in the figure, are structured similarly.
By providing the N-type well region
20
with the boosted output voltage Vout from the charge pump device, the N-type well region
20
is reverse biased against the P-type well regions
31
and
32
in a steady state.
However, it has turned out that when the P-type well regions
31
and
32
are formed in a single N-type well region
20
as described above, a phenomenon like a latch up occurs and the output voltage Vout is hardly boosted. The inventors estimate the cause of the occurrence of the phenomenon as described below.
First, a parasitic thyristor is formed between the neighboring P-type well regions
31
and
32
. That is, a vertical NPN transistor Tr
1
and a lateral PNP transistor Tr
2
are formed as shown in
FIG. 20
, where an emitter of the vertical NPN transistor Tr
1
is made of the drai

Affiliated with

Also associated with

Rating

Large current capacity semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Large current capacity semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Large current capacity semiconductor device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3311034