Lanthanum oxide-based dielectrics for integrated circuit...

Details Lanthanum oxide-based dielectrics for integrated circuit... Lanthanum oxide-based dielectrics for integrated circuit...

2003-01-13

2004-06-22

Coleman, W. David (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S516000, C257S532000

Reexamination Certificate

active

06753567

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to integrated circuit field effect transistors and fabricating methods therefor, and more particularly to gate dielectrics for integrated circuit field effect transistors and fabricating methods therefor.
BACKGROUND OF THE INVENTION
Integrated circuit Field Effect Transistors (FETs) are widely used in microprocessor, logic, memory and/or other integrated circuit devices. As is well known to those having skill in the art, an Insulated Gate integrated circuit Field Effect Transistor (IGFET), often referred to as a Metal Oxide Semiconductor (MOS) device or MOSFET device, includes spaced apart source and drain regions in an integrated circuit substrate and an insulated gate on the integrated circuit substrate therebetween, wherein the insulated gate includes a gate dielectric on the integrated circuit substrate and a gate electrode on the gate dielectric opposite the integrated circuit substrate. Complementary (n-channel and p-channel) insulated gate integrated circuit field effect transistors also are widely used, wherein at least one n-channel MOSFET and at least one p-channel insulated gate field effect transistor are integrated in an integrated circuit substrate. These complementary MOSFETs also are referred to as Complementary Metal Oxide Semiconductor (CMOS) devices.
As the integration density of integrated circuit field effect transistors continues to increase, it may be desirable to reduce the thickness of the gate dielectric layer. A thinned gate dielectric layer can maintain or increase the capacitance density, notwithstanding the shrinking device dimensions. Unfortunately, as the gate dielectric layer continues to be made thinner, leakage current may increase dramatically. For example, for silicon dioxide (SiO
2
) dielectric layers that are commonly used in integrated circuit field effect transistors, below approximately 30 Å in thickness, for each 2 Å reduction in thickness, the leakage current may increase by approximately one order of magnitude. Accordingly, it may be difficult to provide ultra-thin gate dielectric layers using conventional materials, without adversely impacting transistor performance.
Attempts have been made to use high dielectric constant layers (having permittivity greater than silicon dioxide) for gate dielectric layers. These high dielectric constant layers can provide greater capacitance for the same thickness as a conventional silicon dioxide layer. Alternatively, a thicker layer of high dielectric constant dielectric can provide capacitance that is equivalent to a thinner silicon dioxide layer. The thicker layer can, in turn, allow reduced leakage currents to be obtained.
Unfortunately, it may be difficult to replace silicon dioxide with other dielectric materials. For example, high dielectric constant materials may degrade other electrical parameters of the field effect transistors, such as flat band voltage and/or mobility. Moreover, interaction between the gate dielectric layer and the underlying integrated circuit substrate as a result of subsequent processing conditions, such as high temperature exposures, may degrade the properties of the gate dielectric layer.
SUMMARY OF THE INVENTION
Embodiments of the present invention provide lanthanum oxide-based gate dielectrics for integrated circuit field effect transistors. The gate dielectric may include a layer comprising lanthanum oxide, preferably amorphous lanthanum oxide. In other embodiments, the layer comprises an alloy of lanthanum oxide and silicon oxide, i.e., a layer comprising (La
2
O
3
)
x
(SiO
2
)
1−x
, where 0<x≦1. In other embodiments, 0.01<x≦1. In yet other embodiments, 0.5<x≦1. In still other embodiments, x=0.5. When x=0.5, the layer corresponds to a layer of lanthanum silicate (La
2
SiO
5
).
Lanthanum oxide-based gate dielectrics may be able to satisfy at least two technology generations beyond which conventional silicon dioxide-based transistors may not be usable, due to its high permittivity. Moreover, lanthanum oxide-based gate dielectrics may be able to provide appropriate chemical reaction resistance and compatibility and/or resistance to crystallization that is desired for highly integrated field effect transistors.
In some embodiments, the layer comprising (La
2
O
3
)
x
(SiO
2
)
1−x
comprises a uniform layer of (La
2
O
3
)
x
(SiO
2
)
1−x
. In other embodiments, the layer includes a first sublayer comprising (La
2
O
3
)
x1
(SiO
2
)
1−x1
, and a second sublayer comprising (La
2
O
3
)
x2
(SiO
2
)
1−x2
, where x1≦x2. The silicon-rich layer preferably is adjacent the substrate. In yet other embodiments, a third sublayer may be provided on the second sublayer, opposite the first sublayer. The third sublayer may comprise (La
2
O
3
)
x3
(SiO
2
)
1−x3
, where x3≦x2.
Embodiments of field effect transistors according to the present invention can include a gate dielectric layer comprising lanthanum oxide, according to any of the above-described embodiments, and a gate electrode that comprises, for example polysilicon (such as degenerately doped polysilicon), Tantalum Nitride (TaN), Platinum (Pt), Ruthenium (Ru), Ruthenium Oxide (RuO), Iridium (Ir), Iridium Oxide (IrO
2
) and/or Tantalum Silicide Nitride (Ta
1−x
Si
x
N
y
). An integrated circuit complementary field effect transistor pair according to embodiments of the invention can include an n-channel insulated gate field effect transistor and a p-channel insulated gate field effect transistor in an integrated circuit substrate, each of which includes a gate dielectric layer comprising lanthanum oxide in any of the above-described embodiments, and a gate electrode. According to embodiments of the present invention, the gate electrode preferably comprises polysilicon, TaN, Ta
1−x
Si
x
N
y
and/or IrO
2
for the n-channel transistors and preferably comprises polysilicon, Pt, Ru, RuO, Ir and/or IrO
2
for the p-channel transistors.
Gate dielectrics for integrated circuit field effect transistors may be fabricated, according to embodiments of the present invention, by evaporating lanthanum on a silicon surface of an integrated circuit substrate. In some embodiments, the lanthanum may be evaporated in the presence of oxygen. In some embodiments, the lanthanum is evaporated directly on a silicon surface of an integrated circuit substrate, whereas in other embodiments, lanthanum is evaporated on a silicon dioxide layer on a silicon surface of an integrated circuit substrate. In yet other embodiments, the lanthanum can be evaporated on a silicon oxynitride (SiON) layer on a silicon surface of an integrated circuit substrate. In order to evaporate lanthanum directly on a silicon surface of an integrated circuit substrate, a native oxide may be removed from the silicon surface of the integrated circuit substrate. In order to evaporate lanthanum on a silicon dioxide layer on a silicon surface of an integrated circuit substrate, a native oxide may be allowed to form on the integrated circuit substrate and/or an oxide layer may be formed on the silicon surface of the integrated circuit substrate, for example by thermal oxidation and/or deposition. In order to evaporate lanthanum on a silicon oxynitride surface on a silicon substrate, the silicon oxynitride layer can be formed by thermal and/or plasma-assisted growth.
In yet other embodiments of the present invention, lanthanum and silicon are co-evaporated on a silicon surface of an integrated circuit substrate. Fluxes are generated to form the desired lanthanum-to-silicon molar ratio.
According to other embodiments of the invention, after evaporation, the lanthanum that is evaporated onto the silicon surface is annealed in a separate annealing step and/or as part of subsequent device fabrication. Annealing may take place at temperatures of less than about 900° C. and also may take place at oxygen partial pressures of between about 2×10
−8
and 2×10
−6
Torr. Higher annealing temperatures and/or different pressures also may

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