Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2006-09-28
2009-08-04
Dang, Khanh (Department: 2111)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S051000, C713S320000
Reexamination Certificate
active
07571271
ABSTRACT:
A buffer is associated with each of a plurality of data lanes of a multi-lane serial data bus. Data words are timed through the buffers of active ones of the data lanes. Words timed through buffers of active data lanes are merged onto a parallel bus such that data words from each of the active data lanes are merged onto the parallel bus in a pre-defined repeating sequence of data lanes. This approach allows other, non-active, data lanes to remain in a power conservation state.
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Bhatt, Ajay V.; Creating a Third Generation I/O Interconnect; Desktop Architecture Labs, Intel Corporation; from www.express-lane.org; pp. 1-11.
Aleksic Milivoje
Goma Sergiu
Pourbigharaz Fariborz
ATI Technologies ULC
Daley Christopher A
Dang Khanh
Vedder Price P.C.
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