Laminated substrate fabricated from semiconductor wafers...

Details Laminated substrate fabricated from semiconductor wafers... Laminated substrate fabricated from semiconductor wafers...

2000-06-12

2002-02-12

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S455000, C438S459000

Reexamination Certificate

active

06346435

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a laminated substrate and, more particularly, to a laminated substrate fabricated from a pair of silicon wafers bonded to each other without contact between a single crystal silicon layer and an insulating layer selectively formed on one of the silicon wafers.
DESCRIPTION OF THE RELATED ART
A laminated substrate structure such as an SOI (Silicon On Insulator) substrate is fabricated through a bonding process, and is appropriate for a semiconductor power device. The laminated substrate is available for a CMOS (Complementary Metal Oxide Semiconductor) device of the next generation.
An intelligent power integrated circuit device contains a power circuit for controlling a large amount of electric power and a peripheral circuit for controlling the power circuit, and the laminated substrate is expected to electrically isolate the peripheral circuit from the power circuit and enhance the reliability of the intelligent power integrated circuit device.
Japanese Patent Publication of Unexamined Application No. 4-29353 discloses a process of fabricating the laminated substrate, and
FIGS. 1A
to
1
C illustrates the prior art process disclosed therein. The prior art process starts with preparation of a lightly-doped n-type silicon substrate
1
. A photo-resist etching mask (not shown) is patterned on the lightly-doped n-type silicon substrate
1
, and the lightly-doped n-type silicon substrate
1
is selectively etched away by using a reactive ion etching technique. As a result, a shallow recess is formed in a surface portion of the lightly-doped n-type silicon substrate
1
, and a step takes place between the bottom surface of the shallow recess and the major surface of the lightly-doped n-type silicon substrate
1
. The photoresist etching mask is stripped off.
The lightly-doped n-type silicon substrate
1
is thermally oxidized, or silicon dioxide is deposited over the entire surface of the lightly-doped silicon substrate
1
. The lightly-doped n-type silicon substrate
1
is covered with a silicon dioxide layer
2
, and the silicon dioxide layer
2
conformably extends over the major surface of the lightly-doped n-type silicon substrate
1
as shown in FIG.
1
A.
Subsequently, the silicon dioxide layer
2
is polished or uniformly etched until the lightly-doped n-type silicon substrate is exposed again, and tile silicon dioxide layer
2
is left in the shallow recess. The silicon dioxide layer
2
is coplanar with the lightly-doped n-type silicon substrate
1
, and forms a flat surface
3
as shown in FIG.
1
B.
Another heavily-doped n-type silicon substrate
4
is prepared, and the flat surface
3
is bonded to the major surface of the lightly-doped n-type silicon substrate
4
as shown in FIG.
1
C. The resultant semiconductor structure is treated with heat, and the heat treatment enhances the unity. The lightly-doped n-type silicon substrate
1
is polished until broken line
5
, and provides a single crystalline silicon layer With a flat major surface.
A trench isolation is formed in the prior art substrate described hereinbefore as follows. An insulating layer is formed on the flat major Surface of the single crystalline silicon layer
1
, and is selectively etched so as to form an insulating pattern (not shown). Using the insulating pattern as an etching mask, alkaline etchant selectively removes the single crystalline silicon layer
1
so as to form a trench (not shown). The trench is formed between an area assigned to a vertical power transistor and an area assigned to a controlling circuit, and further divides the area assigned to the controlling circuit into active areas for fabricating circuit components.
The resultant semiconductor structure is thermally oxidized so as to grow silicon dioxide, or silicon dioxide is deposited through a low-temperature chemical vapor deposition. As a result, inner surfaces defining the trench are covered with a thin silicon dioxide layer (not shown). Polysilicon is deposited over the entire surface of the resultant semiconductor structure by using a chemical vapor deposition. The polysilicon fills the secondary trench defined by the thin silicon dioxide layer, and swells into a polysilicon layer (not shown) over the major surface of the single crystalline silicon layer. The polysilicon layer and the thin silicon dioxide layer are uniformly removed until tile single crystalline silicon layer
1
is exposed, again, by using a polishing or an etching, and the remaining silicon dioxide layer and the remaining polysilicon form a trench isolation in tile trench.
Another laminated substrate is disclosed in Japanese Patent Application No. 6-156451, and
FIGS. 2A
to
2
C illustrate the prior art process for fabricating a laminated substrate. The process starts with preparation of a lightly-doped n-type single crystalline silicon substrate
6
. The major surface of the lightly-doped n-type single crystalline silicon substrate is thermally oxidized so as to form a silicon oxide layer (not shown), which is uniform in thickness. A photo-resist etching mask (not shown) is patterned on the silicon oxide layer, and the silicon oxide layer is selectively removed by using a dry etching. Thereafter, using the remaining silicon oxide layer as an etching mask, the lightly-doped n-type single crystalline silicon substrate
6
is partially etched away so as to form a shallow recess, and a step takes place between the bottom surface of the shallow recess and the major surface of the lightly-doped n-type single crystalline silicon substrate
6
. The remaining silicon oxide layer is etched away.
Insulating material is deposited over the entire surface of the resultant semiconductor structure. The insulating material fills the shallow recess, and swells into an insulating layer
7
over the major surface of the lightly-doped n-type single crystalline silicon substrate
6
as shown in FIG.
2
A.
The insulating layer
7
is uniformly polished or etched away until the lightly-doped n-type single crystalline silicon substrate
6
is exposed. The insulating layer
7
is left in the shallow recess, and the upper surface of the insulating layer
7
is coplanar with the major surface of the lightly-doped n-type single crystalline silicon substrate
6
.
Polysilicon is deposited over the entire surface of the resultant semiconductor structure, and forms a polysilicon layer
8
. The polysilicon layer
8
is polished, and a smooth surface
9
is created through the polishing as shown in FIG.
2
B.
A heavily-doped n-type silicon substrate
10
is bonded to the smooth surface
9
as shown in
FIG. 2C
, and the lightly-doped n-type single crystalline silicon substrate
6
is polished until broken line
11
so as to regulate the lightly-doped n-type single crystalline silicon layer
6
to a target thickness.
A trench isolation is formed in the prior art substrate described hereinbefore as follows. An insulating layer is formed on the flat major surface of the single crystalline silicon layer
6
, and is selectively etched so as to form an insulating pattern (not shown). Using the insulating pattern as an etching mask, alkaline etchant selectively removes the single crystalline silicon layer
6
so as to form a trench (not shown). The trench is formed between an area assigned to a vertical power transistor and an area assigned to a controlling circuit, and further divides the area assigned to the controlling circuit into active areas for fabricating circuit components.
The resultant semiconductor structure is thermally oxidized so as to grow silicon dioxide, or silicon dioxide is deposited through a low-temperature chemical vapor deposition. As a result, inner surfaces defining the trench are covered with a thin silicon dioxide layer (not shown). Polysilicon is deposited over the entire surface of the resultant semiconductor structure by using a chemical vapor deposition. The polysilicon fills the secondary trench defined by the thin silicon dioxide layer, and swells into a polysilicon layer (not shown) over the major surface of the

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