Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-02-13
2002-06-11
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S383000, C257S384000, C257S385000, C257S412000
Reexamination Certificate
active
06404021
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a laminated structure or multi-layer structure such as a gate electrode formed on a processing target comprising a semiconductor substrate or a glass substrate, and a method of forming the same.
In general, in steps of manufacturing a semiconductor integrated circuit, a desired element or elements are obtained by repeatedly performing film formation, pattern etching, and the like on a semiconductor wafer or a glass plate as a processing target.
For example, when a gate element for an MOSFET is formed on the surface of the wafer, impurities of one conductive type are diffused into positions where a source region
2
and a drain region
4
should be formed, in a wafer W, and a gate oxide film
6
made of, for example, SiO
2
is formed on the area between the positions on the surface of the wafer while a source-drain channel is formed below the gate oxide film
6
, as shown in FIG.
7
A. Further, a gate electrode
8
made of a conductive film is formed on the gate oxide film
6
, to form a transistor.
In recent days, the gate electrode
8
does not have a single-layer structure but has a multi-layer structure and has a two-layer structure in most cases, in consideration of conductivity. For example, a gate electrode
8
is formed by sequentially layering a poly-crystal silicon layer
10
doped with phosphorus and a metal silicide layer such as a tungsten silicide layer
11
, on a gate oxide film
6
.
In accordance with down-sizing and high-integration of a semiconductor integrated circuit in recent days, the processing line width and the gate width are narrowed more and more and the film thickness tends to be thinner and thinner in response to demands for multi-layering. Even though the line width is narrowed, it is demanded that electric characteristics of respective layers and interlayer electric characteristics should maintain conventional performances or attain higher performances. In response to such demands, the gate electrode
8
adopts a two-layer structure consisting of poly-crystal silicon
10
doped with phosphorus and tungsten silicide
11
.
A film made of silicon material, e.g., a poly-crystal silicon layer
10
doped with phosphorus tends to easily form a natural oxide film
14
as shown in
FIG. 7B
on its own surface when exposed to air, moisture, or the like. If a tungsten silicide layer
11
as a next layer is layered on the silicon layer
10
with such a natural oxide film adhered, tightness of a contact between both of the layers
10
,
11
is degraded or sufficient electric conductivity cannot be maintained therebetween, resulting in a problem that the electric characteristics are degraded.
Film formations of the poly-crystal silicon layers
10
are normally carried out by batch processing in which wafers are treated in units each consisting of a number of wafers, e.g., 150 wafers, while film formations of a tungsten silicide layers
11
are carried out by piece-by-piece processing in which film formations are carried out for every wafer. As a result, the time for which one wafer is exposed to air varies between wafers, and the thickness of the natural oxide film varies accordingly. Therefore, wet washing is carried out, for example, with use of HF-based paper immediately before layering the tungsten silicide layer
11
, in order to remove the natural oxide film
14
sticking to the poly-crystal silicon layer
10
.
However, even when wet washing is carried out immediately before layering the tungsten silicide layer
11
, it is very difficult to completely remove the natural oxide film
14
once adhered to the surface of the poly-crystal silicon layer
10
, without affecting a subbing layer (i.e., the poly-crystal silicon layer
10
) below the natural oxide film
14
.
In this respect, there has been a proposal of a method in which a poly-crystal silicon layer
10
doped with phosphorus is formed on a semiconductor wafer in a chamber with use of a cluster tool formed, for example, by concentrating a plurality of chambers with air-tightness maintained between each other, and thereafter, the semiconductor wafer is introduced into another chamber in the same cluster tool, to form a tungsten silicide layer
11
, without exposing the semiconductor wafer to air, i.e., without allowing any natural oxide film to have an opportunity to stick to the wafer (ref. Japanese Patent Application KOKAI Publication No. 9-17705).
As described above, if the tungsten silicide layer
11
is sequentially formed without exposing the wafer to air after the poly-crystal silicon layer
10
doped with phosphorus is formed, no oxide film is formed on the way of the manufacturing steps, and therefore, the entire gate electrode has a low resistance. It is possible to respond to design rules strictly limited under down-sizing and high integration.
In this case, however, phosphorus doped in the poly-crystal silicon layer
10
unevenly rediffuses into the upper tungsten silicide layer
11
through an interface between both of these layers, and therefore, phosphorus is unevenly distributed near the surface of the tungsten silicide layer (e.g., between MOSFETs formed in each wafer), resulting in another problem that the electric characteristic is degraded and/or varies. Also, as a result of this, variation appears between wafers and the manufacturing yield is degraded.
If only a slight portion or portions of natural oxide film can remain on the surface of the poly-crystal silicon layer
10
doped with phosphorus after wet washing is carried out to remove the natural oxide film, the slight portion or portions of natural oxide film prevent phosphorus from diffusing into the upper layer, resulting in no problems. However, when sequential film formation is carried out so that no natural oxide film sticks in response to demands for a low resistance required for down-sizing, a new problem of uneven diffusion of phosphorus as described above appears.
In this respect, explanation will be made in more details with reference to a graph shown in FIG.
8
.
FIG. 8
is a graph showing a resistance of a gate electrode with respect to a phosphorus density of a poly-crystal silicon layer and dependence of a variation rate of the resistance, where the longitudinal axis represents the resistance and the lateral axis represents the phosphorus density of the poly-crystal layer. In this figure, a broken line A shows a case where a tungsten silicide layer
11
is formed after the poly-crystal silicon layer
10
doped with phosphorus at a phosphorus density represented by the lateral axis is formed and is thereafter exposed to air to apply thereto a natural oxide film. A continuous line B shows a case where a tungsten silicide layer
11
is formed without exposing a poly-crystal silicon layer
10
to air after the poly-crystal silicon layer
10
is formed. In the figure, black circles show average values of resistance at phosphorus densities, respectively, and lines extending vertically from the black circles as the centers indicate a variation rate (width). As is apparent from the graph, in the case of the broken line A, the resistance is slightly high while variation of the resistance is small and uniform. Hence, it is found that diffusion of phosphorus into the tungsten silicide layer is blocked by a natural oxide film. In contrast, in the case of the continuous line B, the resistance decreases as the phosphorus density increases while the variation rate of the resistance increases much more. Hence, it is found that phosphorus unevenly diffuses into the tungsten silicide layer and this case is not preferable for characteristics.
FIGS. 9A and 9B
are graphs for recognizing action of phosphorus where the left longitudinal axis represents the resistance of the tungsten silicide layer, the right longitudinal axis represents the uniformity of the resistance, and the lateral axis represents a wafer number.
FIG. 9A
is a graph showing the sheet resistance of the tungsten silicide layer of a gate electrode with respect to 25 pieces of wafers and the uniformity the
Hashimoto Tsuyoshi
Koizumi Masato
Matsuse Kimihiro
Okubo Kazuya
Takahashi Tsuyoshi
Fenty Jesse A.
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Tokyo Electron Limited
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