Laminated semiconductor package

Details Laminated semiconductor package Laminated semiconductor package

2007-10-30

2007-10-30

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S777000

Reexamination Certificate

active

11423597

ABSTRACT:
A laminated semiconductor package includes: a first package having: an insulating layer; a first semiconductor chip embedded in the insulating layer; a wiring connected to the first semiconductor chip; a first connecting section which is formed on a first face side of the insulating layer and connected to the wiring; and a second connecting section which is formed on a second face side of the insulating layer and connected to the wiring, the second face side being opposite to the first face side; and a second package having: a second semiconductor chip; and a third connecting section connected to the second semiconductor chip. In the laminated semiconductor chip, the first package and the second package are laminated one on the other, and the second connecting section and the third connecting section are connected to each other.

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patent: 2005-072596 (2005-03-01), None

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