Laminated integrated circuit package

Details Laminated integrated circuit package Laminated integrated circuit package

1998-05-07

2000-10-31

Thomas, Tom

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

257738, 257780, 257668, 257680, 257683, 257737, 257747, 257795, 257779, 438108, 438612, 438613, H01L 2940

Patent

active

061407070

ABSTRACT:
A low-cost integrated circuit package is provided for packaging integrated circuits. In preferred embodiments, the package comprises a flexible circuit that is laminated to a stiffener using a dielectric adhesive, with the conductive traces on the flexible circuit facing toward the stiffener but separated therefrom by the adhesive. The conductive traces include an array of flip-chip attachment pads. A window is formed in the stiffener over the attachment pad array, such as by etching. The adhesive is then removed over the attachment pads by laser ablation, but left in place between the pads, thus forming a flip-chip attachment site. In preferred embodiments, this invention eliminates the need for high-resolution patterned adhesive, and it also eliminates the need for application of a solder mask at the flip-chip attachment site, because the remaining adhesive performs the solder mask function of preventing bridging between attachment pads. This package provides a die attachment site having a high degree of planarity due to tensile stresses formed in the flexible circuit and adhesive layers during lamination of those layers to the stiffener. Embodiments of this invention may be used with TBGA, frangible lead, and other packaging technologies.

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