Laminated-chip semiconductor device

Details Laminated-chip semiconductor device Laminated-chip semiconductor device

2005-03-01

2005-03-01

Zarneke, David A. (Department: 2829)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S777000, C257S685000, C257S723000

Reexamination Certificate

active

06861738

ABSTRACT:
There is disclosed a laminated-chip semiconductor device which comprises two chip-mounting substrates on each of which at least one semiconductor chip having a plurality of terminals for signals is mounted, and a plurality of chip connecting wirings electrically connected to the terminals for signals of the each semiconductor chip which are mounted on the chip-mounting substrates are formed in a same pattern, and which are laminated along a thickness direction, and one intermediate substrate which is arranged between the two chip-mounting substrates, and in which a plurality of interlayer connecting wirings electrically connected to each of the plurality of chip connecting wirings of the adjacent chip-mounting substrate are formed in a predetermined wiring pattern.

REFERENCES:
patent: 5394010 (1995-02-01), Tazawa et al.
patent: 10-107205 (1998-04-01), None
patent: 2002-510148 (2002-04-01), None
patent: 2001-34154 (2001-04-01), None
Imoto; “Semiconductor Device and Manufacturing Method Thereof”; U.S. Appl. No. 09/648,373, filed Aug. 25, 2000.

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