Laminate substrate and semiconductor package utilizing the...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With contact or lead

Reexamination Certificate

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Details

C257SE23063, C257S684000, C257S779000, C257S786000, C174S255000, C438S125000

Reexamination Certificate

active

07919851

ABSTRACT:
A laminated substrate and the semiconductor package utilizing the substrate are revealed. The laminated substrate primarily comprises a core layer, a first metal layer and a first solder mask disposed on the bottom surface of the core layer, and a second metal layer and a second solder mask disposed on the top surface of the core layer. The two solder masks have different CTEs to compensate potential substrate warpage caused by thermal stresses. Therefore, the manufacturing cost of the substrate can be reduced without adding extra stiffeners nor changing thicknesses of semiconductor packages to suppress substrate warpage during packaging processes. Especially, a die-attaching layer partially covers the second solder mask by printing and is planar after pre-curing for zero-gap die-attaching.

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