Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2011-06-21
2011-06-21
Le, Vu A (Department: 2824)
Static information storage and retrieval
Floating gate
Multiple values
C365S185170
Reexamination Certificate
active
07965549
ABSTRACT:
A semiconductor integrated circuit device includes a memory cell array. In the memory cell array, first memory cells of floating gate type are mixed with second memory cells of floating gate type. The second memory cell is sandwiched between the first memory cells. The first memory cells of floating gate type are configured to store m-level data, where m is a natural number of 2 or more. The second memory cells of floating gate type is configured to store n-level data, where n is a natural number greater than m.
REFERENCES:
patent: 6064591 (2000-05-01), Takeuchi et al.
patent: 7539053 (2009-05-01), Kanda
patent: 2006/0202257 (2006-09-01), Kutsukake et al.
patent: 2008/0112221 (2008-05-01), Park et al.
patent: 2008/0205148 (2008-08-01), Kanda
patent: 2004-192789 (2004-07-01), None
patent: 1999013057 (1999-02-01), None
Korean Office Action dated Jan. 28, 2009.
Kabushiki Kaisha Toshiba
Le Vu A
Pearne & Gordon LLP
LandOfFree
Semiconductor integrated circuit device and method of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor integrated circuit device and method of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor integrated circuit device and method of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2679930