Ladder type clock network for reducing skew of clock signals

Details Ladder type clock network for reducing skew of clock signals Ladder type clock network for reducing skew of clock signals

2001-05-25

2002-11-19

Callahan, Timothy P. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S269000, C327S283000, C327S297000, C365S233100

Reexamination Certificate

active

06483364

ABSTRACT:

This application relies for priority upon Korean Patent Application No. 2000-55204, filed on Sep. 20, 2000, the contents of which are herein incorporated by reference in their entirety.
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit, and more particularly to a clock network for reducing the skew of clock signals.
In semiconductor integrated circuits, an external clock signal input to one pin is converted into a plurality of internal clock signals that propagate along different paths throughout the entire device. The internal clock signals are ideal when they have the same slew rates and duties, and have no skew. However, internal clock signals that are distant from a clock input pin can be delayed more than internal clock signals next to the clock input pin. This is an important issue in high speed operation of semiconductor integrated circuits, and so a phase blending method has been developed to solve the problem.
FIG. 1
illustrates a conventional clock network in which a phase blending method is implemented. As shown in
FIG. 1
, the clock network
100
is a U-shaped clock network that receives an input clock signal CLK and generates a plurality of internal clock signals ICLK
i
(where i is a number between 1 and 9). The input clock signal CLK is connected to a plurality of serially-connected first delay devices
110
a
through
110
f
through a buffer
101
, and the outputs of the delay devices
110
a
through
110
e
are connected to phase blenders
140
a
through
140
e
, respectively. The last delay device
110
f
is in turn connected to a plurality of serially-connected second delay devices
130
a
through
130
f.
The first delay devices
110
a
through
110
f
and the second delay devices
130
a
through
130
f
are manifested as the impedance of a line, e.g., a metal line.
Outputs of the first delay devices
110
a
through
110
e
and the second delay devices
130
a
through
130
e
are input to respective phase blenders
140
a
through
140
e
. Outputs of the phase blenders
140
a
through
140
e
provide the internal clock signals ICLK
i
.
The first internal clock signal ICLK
1
is determined by the phase blender
140
a
as an intermediate waveform between a signal of a first up node UP
1
, i.e., the signal output from the first delay device
110
a
, and a signal of the first down node DN
1
, i.e., the signal output from the second delay device
130
a
. In operation, the signal of a first down node DN
1
has passed the first up node UP
1
, the first delay devices
110
b
through
110
f
, and the second delay devices
130
a
through
130
e.
The second through ninth internal clock signals ICLK
i
(where i is a number between 2 and 9) are generated in a similar manner.
The phase blenders
140
a
through
140
e
are disclosed in B.W. Garlepp, “Portable Digital DLL for High Speed Interface”, IEEE, Journal of Solid State Circuits, May 1999. The phase blender of this article is stable in a state in which two received clock signals slope slightly. However, when the clock signals have a greater slope, jitter is generated in the clock signals.
In addition, since loads of the first delay devices
110
a
through
110
f
and the second delay devices
130
a
through
130
f
are different, a delay of the clock signals input to the phase blenders
140
a
through
140
e
is nonlinear. Furthermore, since the phase blenders
140
a
through
140
e
operate nonlinearly, a delay of the clock signals is even more nonlinear. As a result, the internal clock signals ICLK
i
are inevitably skewed. Since the blended rate in the phase blenders
140
a
through
140
e
changes with the variation in the power supply voltage, the temperature, and the semiconductor device manufacturing process, the range of a skew value is similarly wide.
Thus, a clock network which is capable of reducing the skew of the internal clock signals ICLK
i
is required.
SUMMARY OF THE INVENTION
To solve the above problems, it is an object of the present invention to provide a clock network for reducing the skew of clock signals.
Accordingly, to achieve the above object, a clock network is provide that comprises a plurality of first delay units connected in a line, each operating to delay a clock signal by a first time; a plurality of buffers connected to respective outputs of the first delay units, the buffers operating to generate internal clock signals; and a plurality of second delay units connected in a line, each second delay unit being connected to an output of a respective one of the plurality of buffers.
In addition, a clock network could also be provided that comprises a buffer for buffering a clock signal; a plurality of first delay units formed in a line for delaying an output of the first buffer by a first time; and a plurality of second delay units connected to respective outputs of the first delay units.
In this clock network, respective outputs of first and second buffers are preferably connected via a plurality of buffers.
A clock network may also be provided that comprises a first buffer for buffering a clock signal; a plurality of first delay units for delaying an output of the first buffer by a first time; a plurality of second buffers connected to respective outputs of the first delay units; and a plurality of second delay units connected to respective outputs of the second buffers.
In each of these clock networks the first and second delay units preferably consist essentially of the resistance and capacitance of lines through which the clock signal propagates. In addition, the first delay units and the second delay units preferably have bilateral output characteristics.
According to the present invention, the skew of the internal clock signals is reduced, and internal clock signals are generated that have a stable duty with respect to a variation in a semiconductor device manufacturing process, temperature, and power supply voltage.


REFERENCES:
patent: 5521599 (1996-05-01), McCarroll et al.
patent: 5572719 (1996-11-01), Biesterfeldt
patent: 5654659 (1997-08-01), Asada
patent: 2000-0040542 (2000-07-01), None

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