Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-01-31
2006-01-31
Sparks, Donald (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S119000, C711S133000, C711S141000, C711S142000, C711S144000, C711S159000, C709S217000, C707S793000, C707S793000
Reexamination Certificate
active
06993631
ABSTRACT:
A first node includes a first cache and a plurality of coherent agents. In response to a transaction to a coherency block by a first coherent agent of the plurality of coherent agents, the first node is configured to fetch the coherency block from another node. The other node is configured to record a state in which the coherency block is provided to the first node. The first cache is designated to store the state of the coherency block recorded by the first node.
REFERENCES:
patent: 5644753 (1997-07-01), Ebrahim et al.
patent: 5710907 (1998-01-01), Hagersten et al.
patent: 5878268 (1999-03-01), Hagersten
patent: 5887138 (1999-03-01), Hagersten et al.
patent: 5920226 (1999-07-01), Mimura
patent: 5925097 (1999-07-01), Gopinath et al.
patent: 5961623 (1999-10-01), James et al.
patent: 5963745 (1999-10-01), Collins et al.
patent: 6009426 (1999-12-01), Jouenne et al.
patent: 6070215 (2000-05-01), Deschepper et al.
patent: 6094715 (2000-07-01), Wilkinson et al.
patent: 6101420 (2000-08-01), VanDoren et al.
patent: 6105119 (2000-08-01), Kerr et al.
patent: 6108739 (2000-08-01), James et al.
patent: 6108752 (2000-08-01), Van Doren et al.
patent: 6108764 (2000-08-01), Baumgartner et al.
patent: 6138217 (2000-10-01), Hamaguchi
patent: 6182201 (2001-01-01), Arimilli et al.
patent: 6195739 (2001-02-01), Wright et al.
patent: 6202132 (2001-03-01), Islam et al.
patent: 6209065 (2001-03-01), Van Doren et al.
patent: 6219755 (2001-04-01), Klein
patent: 6249846 (2001-06-01), Van Doren et al.
patent: 6266731 (2001-07-01), Riley et al.
patent: 6266743 (2001-07-01), Carpenter et al.
patent: 6279085 (2001-08-01), Carpenter et al.
patent: 6298370 (2001-10-01), Tang et al.
patent: 6338122 (2002-01-01), Baumgartner et al.
patent: 6546429 (2003-04-01), Baumgartner et al.
patent: 6725343 (2004-04-01), Barroso et al.
patent: 2001/0039604 (2001-11-01), Takahashi
patent: 2002/0038407 (2002-03-01), Mounes-Toussi et al.
patent: 265 636 (1986-10-01), None
patent: 893 766 (1999-01-01), None
patent: 936 555 (1999-08-01), None
patent: 945 805 (1999-09-01), None
patent: 777 179 (2002-05-01), None
patent: WO 00/38069 (2000-06-01), None
Daniel E.Lenoski, The Design and Analysis of DASH: A Scalable Directory-Based Multiprocessor, Dec. 1991, A Dissertation submitted to the Department of Electrical Engineering and The Committee on Graduate Studies of Stanford University, pp 1-176.
European Search Report for BP12P037EP (02025692.1-2416-), mailed May 16, 2003, 3 pages.
“They Design and Analysis of Dash: A Scalable Directory-Based Multiprocessor,” Daniel Lenoski, Dec. 1991, A Dissertation submitted to the Dept. of Elect. Engin. And the committee on graduate studies of Stanford Univ., 176 pages.
“An Argument for Simple COMA,” Saulsbury, et al., Aug. 1, 1994, SISC Research Report Number: R94:15, 20 pages.
Tom R. Halfhill, “SiByte Reveals 64-Bit Core For NPUs; Independent MIPS64 Design Combines Low Power, High Performance,” Microdesign Resources, Jun. 2000, Microprocessor Report, 4 pages.
SiByte, “Target Applications,” http://sibyte.com/mercurian/applications.htm, Jan. 15, 2001, 2 pages.
SiByte, “SiByte Technology,” http://sibyte.com/mercurian/technology.htm, Jan. 15, 2001, 3 pages.
SiByte, “The Mercurian Processor,” http://sibyte.com/mercurian, Jan. 15, 2001, 2 pages.
SiByte, “Fact Sheet,” SB-1 CPU, Oct. 2000, rev. 0.1, 1 page.
SiByte, “Fact Sheet,” SB-1250, Oct. 2000, rev. 0.2, 10 pages.
Stepanian, SiByte, SiByte SB-1 MIPS64 CPU Core, Embedded Processor Forum 2000, Jun. 13, 2000, 15 pages.
Jim Keller, “The Mercurian Processor: A High Performance, Power-Efficient CMP for Networking,” Oct. 10, 2000, 22 pages.
EP app 02025691.3, Broadcom Corp.
Giorgi et al.; PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors; IEEE Transactions on Parallel and Distributed Systems; vol. 10, No. 7, Jul. 1999.
Broadcom Corporation
Garlick Harrison & Markison LLP
Sparks Donald
Truong Bao Q.
LandOfFree
L2 cache maintaining local ownership of remote coherency blocks does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with L2 cache maintaining local ownership of remote coherency blocks, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and L2 cache maintaining local ownership of remote coherency blocks will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3573750