L2 cache controller with slice directory and unified cache...

Details L2 cache controller with slice directory and unified cache... L2 cache controller with slice directory and unified cache...

2011-08-16

2011-08-16

Elmore, Stephen (Department: 2185)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S129000, C711S156000, C711S173000

Reexamination Certificate

active

08001330

ABSTRACT:
A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first directory to access the first array slice while using a second directory to access the second array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In one embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. The cache array is arranged with rows and columns of cache sectors wherein a cache line is spread across sectors in different rows and columns, with a portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency.

REFERENCES:
patent: 5896548 (1999-04-01), Ofek
patent: 6408362 (2002-06-01), Arimilli et al.
patent: 6442653 (2002-08-01), Arimilli et al.
patent: 6625696 (2003-09-01), Willke, II
patent: 6769081 (2004-07-01), Parulkar
patent: 6859862 (2005-02-01), Liao et al.
patent: 7469318 (2008-12-01), Chung et al.
patent: 2002/0065988 (2002-05-01), Lasserre et al.
patent: 2003/0110339 (2003-06-01), Calvignac et al.
patent: 2004/0205275 (2004-10-01), Bell, Jr. et al.
patent: 2004/0205362 (2004-10-01), Catherman et al.
patent: 2004/0215888 (2004-10-01), Arimilli et al.
patent: 2005/0086509 (2005-04-01), Ranganathan
patent: 2005/0137889 (2005-06-01), Wheeler
patent: 2005/0172091 (2005-08-01), Rotithor et al.

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