Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-04-26
2004-04-27
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C714S030000, C714S724000
Reexamination Certificate
active
06728938
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to failure analysis of integrated circuits and more particularly to knowledge-based failure analysis of integrated circuits.
2. Description of the Related Art
It is known to test and fault isolate a semiconductor integrated circuits (IC's) using a visual scan of the potentially faulty locations on the chip. Probes are utilized after a visual scan has been performed on the chip using a microscope. Such a visual scan over large portions of a 75,000 to over 100,000 gate chip is exceptionally time consuming and potentially error prone.
If an error is detected in a circuit, it is often difficult to isolate the exact location of the malfunctioning element. Testing procedures that have been employed to test ICs include transmitting data through the circuit and reading data output from the circuit.
Improving the testing time required for integrated circuits requires isolation of the faults on a chip to as small an area as possible. The cause of the fault may then be quickly determined if a small enough area can be isolated. Ideally, a single location should be isolated so that the cause of the failure can be visually determined with little time or effort.
Accordingly, it is know to perform analysis of a system by providing a set of inputs and then reading the state of every flip-flop within the system, this analysis is commonly referred to as full scan dump processing. The advent of VLSI/ULSI technology causes the number of flip-flops in an integrated circuit to double every three years. Therefore, the amount of VLSI/ULSI full scan data is doubled every three years. Based on current technology, there are about 80,000 flops in a typical high performance microprocessor such a an UltraSparc III processor. This number will likely become 160,000 within three years. The more than 80,000 bits of information is a huge amount of data for designers to utilize and analyze.
It is difficult for human beings to process such a large amount of raw data. Traditionally, each bit of the raw data is annotated with the associated flop-flop name. The size of an annotated full scan dump is usually 8-10 times larger than that of the raw data. For the UltraSparc III processor, the size of a full scan dump exceeds 650 k-byte. To diagnose a failure with such a large size full scan dump is a difficult and error prone task.
SUMMARY OF THE INVENTION
In accordance with the present invention, a systematic methodology to analyze a full scan dump is presented. The methodology is knowledge-based, i.e., the methodology intelligently processes a full scan dump using knowledge of the system from which the full scan is obtained.
More specifically, in a preferred embodiment, the present invention relates to a method for processing a scan dump of an integrated circuit which includes a scan to the integrated circuit that provides a scan dump. The scan dump is processed to determine whether any errors are present. If an error is present, information is provided to generate another scan of the integrated circuit. Information from intelligently checking the scan dump is extracted based upon knowledge of the integrated circuit.
The present invention relates to a scan dump analysis system for analyzing a scan dump of an integrated circuit which includes: means for providing a scan to the integrated circuit, the integrated circuit providing a scan dump; means for extracting information from the scan dump based upon knowledge of the integrated circuit; means for processing the scan dump to determine whether any errors are present in the scan dump; means for intelligently checking the scan dump based upon knowledge of the integrated circuit; and, means for providing information to generate another scan of the integrated circuit, if an error is determined to be present.
The present invention relates to a scan dump analysis system for analyzing a scan dump of an integrated circuit which includes a knowledge-based extractor portion and an intelligent checker portion. The knowledge based extractor portion extracts information from the scan dump based upon knowledge of the integrated circuit. The intelligent checker portion processes the scan dump to determine whether any errors are present and checks the scan dump, based upon knowledge of the integrated circuit, to determine what part of the integrated circuit caused the error to be present. The intelligent checker provides information to generate another scan of the integrated circuit if an error is determined to be present.
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Hamilton & Terrile LLP
Siek Vuthe
Terrile Stephen A.
LandOfFree
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