Static information storage and retrieval – Read/write circuit – Including level shift or pull-up circuit
Reexamination Certificate
2001-08-17
2003-04-01
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including level shift or pull-up circuit
C365S230060, C365S233500
Reexamination Certificate
active
06542415
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to accessing a memory device, and more particularly, to a signal generator for generating memory access signals used to access a memory device for improves performance.
BACKGROUND OF THE INVENTION
As processing system performance increases, a corresponding increase in memory performance is required. In order to meet past performance demands, burst mode memory operation was introduced. During burst mode operation, the memory operates with a synchronizing clock to access multiple sequential memory locations. For example, during a burst mode read operation, the synchronizing clock is used to read sequential memory locations while clocking out previously read data every clock cycle. Using this technique, high data transfer rates can be realized. Recently, however, even higher memory performance has become a requirement.
Since burst mode operation is a sequential operation, during memory accesses cell row addresses do not change until the end of an internal column address is reached. Usually the memory power source voltage (Vcc) is not high enough to turn on a core cell that may have a threshold voltage (Vt) of approximately 2.5 volts. To create a sufficient word line voltage to access the core cell, the Vcc voltage is boosted. Since a word line does not switch until the internal address hits the end of the column address, the word line voltage boosting circuit does not have to switch until the end of the internal column address is reached.
As for core data access operations, assuming that there are a set of two sense amplifiers (SYA) devices that use two clock cycles to output data from the core, an address detection signal (ATD) used to detect address changes, is generated every two clocks. Usually the boost operation is triggered by the ATD signal, so typical boost circuits are designed to detect and use the ATD signal to trigger the boost.
FIG. 1
shows a typical boost circuit
102
used to boost the voltage of a memory word line signal. The boost circuit
102
is shown coupled to a decoder
104
that produces a word line output signal
106
by decoding address input
107
. When the kickb signal is at a high level, the booster output voltage (Vb) at output node Nb is set to the level of Vcc by n-channel depletion transistor
108
. When the kickb signal goes low, then a boosting of the signal Vb occurs and is expressed as:
Vb=
((
Cb/
(
Cb+Cd
))+1)*
Vcc
where Cd is the capacitive effect of the decoder as shown at
110
.
FIG. 2
shows signal timing of signals associated with the boost circuit of FIG.
1
. Address signals are shown to describe the generation of the kickb signal. Every time address signal A
0
is at a high level and the rising edge of clock (CLK) occurs, an ATD signal is generated. The ATD signal is also generated when all of the addresses are high, as indicated by the “last column Ad” signal, and a rising edge of the CLK occurs. This ATD signal generates the kickb signal that is used to reset and activate the boosting signal, as shown by the waveform associated with Vb. In order to realize this signal timing, it is necessary to have an ATD generator to generate the ATD signal that is used to generate the kickb signal that is used to execute the subsequent reset and boosting operation.
FIG. 3
shows a typical ATD generator circuit
300
. When the clock (CLK) signal goes to a high level (rising edge) while address bit A
0
is at a high level, the signal level at node “a” goes to a low level, and as a result, the ATD signal will be triggered so that a high level will appear at output
302
. After the signal at the node “a” propagates through a delay element, a signal at node “b” goes to a low level to terminate the ATD signal so that a low level then appears at the output
302
. Thus, the address bit A
0
and the clock signal (CLK) are used to generate the ATD signal.
FIG. 4
shows a typical boost trigger circuit
400
. The boost trigger circuit
400
receives the ATD signal from the ATD generator circuit
300
and generates a kickb signal that triggers the reset and boost operation. When CLK signal goes to a high level while all of column addresses are high, then the signal at node Bt goes to a high level. In this state, if the ATD signal goes to a high level, the kickb signal goes high to reset the boost circuit (see FIG.
1
). When the ATD signal goes to a low level, the kickb signal goes to a low level and triggers the boost function.
In the circuit of
FIG. 4
, the kickb signal is generated with AND logic that combines the Bt and ATD signals. However, since the main goal of the burst mode architecture is to improve memory performance, as memories become faster and faster the kickb signal needs to have a correspondingly fast activation time. One problem with the above described kickb generation circuits is that they have speed limitations in that there are delays associated with the generation and combination of the Bt and ATD signals. These delays may slow the generation of the kickb signal. For example, capacitive loading on the ATD line may slow the ATD signal and ultimately delay the generation of the kickb signal, and thus limit the operational speed of the memory.
Therefore, it is desirable to have a way to generate a kickb signal to reset and trigger the boost operation of a memory device, where the generation of the kickb signal does not suffer from delays associated with detecting and combining the Bt and ATD signals.
SUMMARY OF THE INVENTION
The present invention includes a system for generating a kickb signal for use with a memory device. The kickb signal is a boost activation signal that is used to reset and activate a boost circuit to boost a memory access signal. For example, the boost circuit boosts a word line signal used during a burst mode memory access. The system generates the kickb signal without introducing time delays associated with conventional circuits, so that increased memory performance is possible. For example, during burst mode operation of a high performance memory device, the system provides fast activation of the kickb signal to allow fast reset of a voltage boosting circuit that boosts the voltage of memory signals used to access core cells of the high performance memory device.
In one embodiment of the invention, a signal generator for generating a kickb signal used to reset a boost signal used to operate a memory device is provided. The signal generator includes an address detector that receives one or more address lines and a clock signal to produce a detector output. A switch circuit is also included that receives the detector output, the clock signal and a feedback signal to produce a switch output. A delay circuit is coupled to receive the switch output to produce a delayed switch output, and an output circuit is provided that is coupled to receive the switch output and the delayed switch output to produce the kickb signal, where the kickb signal forms the feedback signal.
REFERENCES:
patent: 4984204 (1991-01-01), Sato et al.
patent: 5459693 (1995-10-01), Komarek et al.
patent: 5596544 (1997-01-01), Komarek et al.
patent: 5907517 (1999-05-01), Komarek et al.
Auduong Gene N.
Coudert Brothers LLP
Nelms David
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